Semiconductor Memory Bit Inversion for Write Efficiency

The patent applies preliminary action by pre-calculating the inverted data pattern before writing to memory. The controller determines which bits need to be inverted based on the current state and desired state, then pre-prepares the inverted data. This allows the write operation to proceed more efficiently by minimizing the actual state changes needed during the memory write process, thereby improving write speed while maintaining nonvolatile storage capability.

The patent applies inversion by flipping the data bits before writing them to memory. When reading, the stored inverted data is inverted again to recover the original data. This technique reduces the number of actual state changes in the variable resistive element because writing inverted data may require fewer or less severe write operations compared to writing the original data pattern directly, thereby reducing cumulative damage from repeated writes while maintaining full rewrite capability.

The patent applies preliminary action by performing error detection and correction operations during the data read process itself, rather than as a separate subsequent step. The read circuit detects errors in the read data and performs correction if needed, then outputs the corrected data. This integration of error handling into the read operation reduces overall processing time while maintaining high data accuracy, as the error checking and correction are performed concurrently with data retrieval rather than sequentially after it.