Memory Refresh Control Circuit for Disturbance Mitigation

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Solution Overview

Problem

In high-speed memory operations, frequent activation of adjacent memory rows leads to data loss due to disturbance, necessitating a novel memory control mechanism to maintain data integrity.

Innovation Solution

A memory device with a refresh control mechanism that monitors and adapts to disturbances by generating intermediate addresses indicating wordline types and determining refresh based on disturbance counts, utilizing both normal and redundant wordlines to reduce data loss.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If frequent row activation is performed to increase operating speed, then productivity is improved, but data integrity deteriorates due to row disturbance

Engineering Contradiction:

Improveoperating speedVSAvoiddata integrity

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The refresh control circuit proactively identifies and refreshes adjacent rows that are likely to be disturbed before data loss occurs. By monitoring activation patterns and predicting which rows will suffer from disturbance, the system performs preliminary refresh operations to prevent data integrity issues rather than reacting after errors occur.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system implements a feedback mechanism where the refresh control circuit continuously monitors row activation patterns and disturbance conditions. Based on this feedback information about which rows are frequently activated and which adjacent rows are at risk, the system dynamically adjusts refresh operations to maintain data integrity while allowing high-speed operation to continue.

Inventive Principle:

Principle #23Feedback

2Reliability

If conventional target row refresh mode is used to maintain data integrity, then reliability is improved, but device complexity increases

Engineering Contradiction:

Improvedata integrityVSAvoidmemory circuitry complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The address structure is segmented into multiple components including intermediate addresses that identify specific wordline types (normal or redundant). This segmentation allows the refresh control circuit to selectively manage different row types and apply appropriate refresh strategies without requiring a complete system redesign or complex control logic for the entire memory array.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The refresh control circuit acts as an intermediary between the row activation operations and the refresh operations. It monitors activation patterns, identifies disturbed rows, and orchestrates refresh operations without requiring direct intervention from higher-level control logic. This intermediary role simplifies the overall system architecture by localizing the complexity within the refresh control circuit itself.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Reliability

If all adjacent rows are refreshed after each activation to prevent data loss, then data integrity is improved, but productivity deteriorates due to excessive refresh overhead

Engineering Contradiction:

Improvedata integrityVSAvoidoperating speed

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

Instead of uniformly refreshing all adjacent rows, the system applies refresh operations selectively to specific rows that are actually at risk of disturbance. The refresh control circuit identifies which adjacent rows have been activated or are likely to be disturbed, and applies refresh operations only to those local areas, leaving other rows untouched and available for normal operation.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The system performs partial refresh operations on only the necessary adjacent rows rather than refreshing all rows. By applying refresh action to just the subset of rows that are disturbed or at risk, the system achieves sufficient data protection without the excessive overhead of blanket refreshing, thereby maintaining high operating speed.

Inventive Principle:

Principle #16Partial or excessive action

Data Source

PatentUS9805782B1Memory device capable of determining candidate wordline for refresh and control method thereof

Publication Date: 2017.10.31 ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC

AI summary

A memory device includes an address generation circuit, an address processing circuit and a refresh control circuit. The address generation circuit generates a first intermediate address according to a row address. The first intermediate address includes a first wordline address and an identification code indicating whether a first wordline indicated by the first wordline address is a normal or redundant wordline. The address processing circuit refers to the first intermediate address to generate a second intermediate address indicating a second wordline adjacent to the first wordline. The second intermediate address includes a second wordline address and an identification code indicating whether the second wordline is a normal or redundant wordline. The refresh control circuit determines a disturbance count of the second wordline each time the first wordline is activated, and refers to the disturbance count to determine whether to output the second wordline address to refresh the second wordline.