STT-MRAM Back-Hopping Correction via Two-Segment Write Pulse

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Solution Overview

Problem

Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) devices face the challenge of back-hopping, where the ferromagnetic pinned layer or free layer experiences unintended magnetization reversal, leading to incorrect switching and reduced write margin due to variations in write currents and resistance across MRAM cells in an array.

Innovation Solution

A method involving a two-segment write pulse is applied to the MRAM cells, with the first segment establishing a high voltage for initial switching and a second segment using a lower voltage to correct any back-hopped states, minimizing the probability of further magnetization reversal and ensuring accurate polarization of the ferromagnetic pinned layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a single high-voltage write pulse is applied to switch the MTJ stack polarization, then the initial switching speed is improved, but back-hopping occurs causing write margin reduction and reliability degradation

Engineering Contradiction:
Improveswitching speedVSAvoidwrite margin
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The write pulse is divided into two segments: a first segment with a first voltage level for initial switching, and a second segment with a second voltage level for correcting back-hopped states. This segmentation allows the system to maintain fast switching while reducing back-hopping errors that degrade write margin and reliability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The first segment of the write pulse is applied beforehand to establish the desired polarization state, and the second segment follows to correct any back-hopped states. This preliminary action ensures that the majority of cells are switched correctly before the correction phase, improving overall write reliability.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If write current is increased to ensure reliable switching across all MRAM cells, then switching reliability is improved, but variations in write current and resistance cause back-hopping and reduce write margin

Engineering Contradiction:
Improveswitching reliabilityVSAvoidwrite margin
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The two-segment write pulse applies different voltage levels to different groups of cells based on their switching state. Cells that successfully switched are maintained in their new state by the second segment, while cells that experienced back-hopping are corrected. This local quality approach addresses variations in write current and resistance across the array without requiring uniformly high current for all cells.

Inventive Principle:
Principle #3Local quality

3Reliability

If a two-segment write pulse is applied to correct back-hopped states, then write margin is improved, but the write operation time increases

Engineering Contradiction:
Improvewrite marginVSAvoidwrite operation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The write operation uses periodic pulsing with two distinct voltage levels applied in sequence. The first segment applies a higher voltage for a shorter duration to initiate switching, and the second segment applies a lower voltage to correct back-hopped states. This periodic action with optimized timing reduces the total write time while maintaining improved write margin through back-hopping correction.

Inventive Principle:
Principle #19Periodic action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces the occurrence of back-hopping, enhancing the write margin and ensuring accurate data storage by correcting unintended polarization changes in the MRAM cells, thereby improving the reliability and performance of STT-MRAM devices.

Implementation Method 1

Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) has a potential of becoming the 'universal' memory combining the non-volatility, fast read/write and high endurance. MRAM chips are made of Magnetic Tunnel Junctions (MTJs), with a typical tri-layer structure: a ferromagnetic free layer which magnetization direction represents the stored memory information, a ferromagnetic pinned layer which magnetization direction is fixed during chip operation to provide spin transfer torque

Methodology Applied
Scientific EffectSpin transfer torque:

Implementation Method 2

a tunnel barrier in between that yield different resistivity for parallel or anti-parallel configuration of the magnetization direction of the ferromagnetic free layer and ferromagnetic pinned layer

Methodology Applied
Scientific EffectTunneling:

Implementation Method 3

since electrons preserve their spin orientation during the tunneling process and can only tunnel into the sub-band of the same spin orientation

Methodology Applied
Scientific EffectSpin orientation preservation:

Data Source

PatentUS10978124B2Method and circuits for programming STT-MRAM cells for reducing back-hopping
Publication Date: 2021.04.13 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US10978124B2 patent drawing
  • US10978124B2 patent drawing
  • US10978124B2 patent drawing

AI summary

Circuits and methods for programming a MTJ stack of an MRAM cell minimizes a ferromagnetic free layer or pinned layer polarization reversal due to back-hopping. The programming begins by applying a first segment of the segment of the write pulse at a first write voltage level for a first time period to program the MTJ stack. A second segment of the segment of the write pulse at a second write voltage level that is less than the first write voltage level is applied to the magnetic tunnel junction stack for a second time period to correct the polarization of the MTJ when the MTJ stack has reversed polarization during the first time period. The second segment of the segment of the write pulse may be a ramp, or multiple ramps, or have a quiescent period between it and the first segment of the write pulse.