Memory Device Write Error Rate Control via Address Transition Detection
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Solution Overview
Problem
Non-volatile random access memory devices face challenges in maintaining low write error rates due to the duration of write operations, which affects the reliability and efficiency of data storage.
Innovation Solution
A memory device design that includes an address transition detector and a control logic circuit to manage word-line-on signals, allowing for either long-kept or divided write operations based on the detection of address changes, optimizing write time to minimize write error rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If write operation duration is extended to improve write reliability, then write error rate decreases, but write speed and productivity deteriorate
Solution Approach 1:
The patent applies dynamics by making the word-line-on signal duration adaptive rather than fixed. The control logic circuit dynamically adjusts the write operation duration based on whether an address transition is detected during the write period. When no address transition occurs, the write operation continues for the full duration to ensure low write error rates. When an address transition is detected, the write operation is terminated early to improve write speed. This dynamic adjustment resolves the contradiction between write reliability and write speed.
2Productivity
If write operation is terminated early on address change to improve speed, then write productivity increases, but write reliability deteriorates
Solution Approach 1:
The patent implements feedback by using the address transition detection result to control the write operation termination. The address transition detector continuously monitors for address changes during the write operation and provides feedback to the control logic circuit. Based on this feedback, the control logic circuit decides whether to terminate the write operation early (improving speed) or continue for the full duration (maintaining reliability). This feedback mechanism resolves the contradiction by making the write operation duration responsive to actual address transition conditions.
3Productivity
If address transition detection is implemented to optimize write operations, then write efficiency improves, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the control function into separate modular components: an address transition detector module and a control logic circuit module. The address transition detector is implemented as a distinct functional unit that can be independently designed and integrated. This segmentation allows the complexity to be managed through modular design, where each component has a specific function, and the overall system benefits from write efficiency optimization without requiring complete redesign of the entire control system.
Data Source
AI summary
A memory device includes a cell array including cells, an address transition detector outputting a transition detection signal as to whether an address of a write command is changed, and a control logic circuit generating one of word-line-on signals for performing a write operation on the cell array in response to the write command, and terminating the write operation in accordance with the transition detection signal. The word-line-on signals include a long-kept word-line-on signal that stays active before the address is changed and a divided word-line-on signal that is, before the address is changed, divided into sub-word-line-on signals.