Auxiliary Branches for SRAM Read Stability and Write Speed
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Solution Overview
Problem
Static random access memory (SRAM) cells face issues with read disturb and write recovery time due to dummy read operations affecting other SRAM cells in the same row, leading to instability and longer write margins.
Innovation Solution
Incorporating data-controlled auxiliary branches that assist cross-coupled inverters during read and write operations, ensuring that auxiliary branches are not conducting during data holding and are conducting during data flipping, thereby reducing the impact of dummy read operations and improving write recovery time and write margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If auxiliary branches are added to assist inverters during read operations, then read static noise margin is improved, but device complexity increases
Solution Approach 1:
The auxiliary branches are made dynamic by controlling them with write word lines. During read operations, the auxiliary branches are activated to provide additional pull-up or pull-down current to assist the cross-coupled inverters in maintaining stable storage nodes, thereby improving read static noise margin. During write operations, the auxiliary branches are deactivated to avoid interfering with the data flipping process. This dynamic control allows the same circuit structure to serve multiple functions without permanently increasing complexity.
Solution Approach 2:
The auxiliary branches serve multiple functions: they assist the cross-coupled inverters during read operations to improve noise margin, and can be deactivated during write operations to allow normal data flipping. The control logic using write word lines integrates the auxiliary branch control into the existing write operation mechanism, making the auxiliary branches a multi-functional component that enhances performance without requiring separate dedicated control circuits.
2Reliability
If auxiliary branches are activated during write operations, then write margin is improved, but write recovery time increases
Solution Approach 1:
The auxiliary branches are dynamically controlled based on the operation phase. During write operations, the auxiliary branches are deactivated (controlled by deasserted write word lines) to allow the cross-coupled inverters to flip data without interference, thereby maintaining fast write recovery time. The auxiliary branches are only activated during read operations when they provide their noise margin assistance function. This temporal separation of functions resolves the contradiction between improving write margin and maintaining fast write recovery.
3Ease of operation
If word line is asserted for read operation, then data sensing is enabled, but dummy read operations affect other SRAM cells causing instability
Solution Approach 1:
The auxiliary branches provide localized assistance to specific cross-coupled inverters during read operations. By controlling the auxiliary branches based on the state of the storage nodes, the circuit provides targeted support to the inverter that needs it most, helping to stabilize the storage node voltage and prevent read disturb effects from propagating to neighboring cells. This localized quality enhancement improves data stability without requiring global changes to the entire SRAM array.
Data Source
AI summary
A method includes: during a read operation of a first storage node and a second storage node formed by cross-coupled inverters, based on data stored in the first storage node and the second storage node, causing a first auxiliary branch or a second auxiliary branch to assist a corresponding one of the cross-coupled inverters in holding data; and during a write operation of the first storage node and the second storage node, based on data to be written to the first storage node and the second storage node, causing the first auxiliary branch or the second auxiliary branch to assist a corresponding one of the cross-coupled inverters in flipping data.