Resistance Variable Memory Read Circuit Handling Drift
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Resistance drift in resistance variable memory devices, such as phase change RAM and ReRAM, affects data retention time and device lifetime, leading to operational failures during read operations.
Innovation Solution
A read circuit unit with a cyclic analog-to-digital conversion (ADC) process is implemented to generate digital codes from cell currents, allowing for flexible handling of resistance drift by using test reference voltages during a test read mode, eliminating the need for storing code values for all memory cells and converting them into data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional read operation is used to sense data by comparing current values, then the read operation can detect stored data, but resistance drift causes operational failures and reduced data retention time
Solution Approach 1:
The patent changes the read operation parameters by implementing a cyclic ADC process that repeatedly converts cell currents to digital codes. Instead of using a single comparison operation, the system performs multiple conversion cycles and uses logic circuitry to determine logical data from the digital codes, making the read operation robust against resistance drift variations
Solution Approach 2:
The patent replaces the conventional current comparison method with an analog-to-digital conversion system. By converting the analog cell current into digital codes through a cyclic ADC process, the system eliminates the need for direct analog comparison, thereby reducing sensitivity to resistance drift and improving operational reliability
2Reliability
If digital codes are generated by repeating cyclic ADC process multiple times, then resistance drift can be handled flexibly and reliability improves, but circuit complexity increases
Solution Approach 1:
The read circuit unit is designed to perform multiple functions: it can operate in normal read mode using the cyclic ADC process, and in test read mode using test reference voltages. This multi-functionality allows the same circuit to handle both regular operations and resistance drift compensation, reducing the need for separate dedicated circuits
Solution Approach 2:
The system uses its own ADC infrastructure and digital processing capabilities to handle resistance drift compensation. By leveraging existing circuit components and making them operate in different modes (normal vs. test read), the patent avoids adding significant external complexity while achieving reliability improvements
3Measurement precision
If test reference voltages are used during test read mode, then resistance drift can be directly compensated, but the read operation becomes more complex
Solution Approach 1:
The patent implements dynamic reference voltage selection where the system can switch between normal reference voltages and test reference voltages based on the operating mode. During test read mode, test reference voltages are used to directly compensate for resistance drift, while normal operations use standard reference voltages, providing adaptability without permanent complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution improves product reliability by directly determining logical data from resistance values, reducing the need for complex circuitry and enabling flexible handling of resistance drift, thus enhancing data retention and operational stability.
Implementation Method 1
an information storage state is defined according to a resistance state of a data storage material
Implementation Method 2
generate a digital code by repeating a cyclic ADC process a designated number of times based on a preset normal reference voltage
Data Source
AI summary
A resistance variable memory apparatus may include: a memory cell array; and a read circuit unit configured to receive a cell current, generate a digital code by repeating a cyclic analog-to-digital conversion (ADC) process a designated number of times, generate read data from the digital code, and output the generated read data during a normal read mode for the memory cell array, and to generate test data corresponding to the cell current and output the generated test data during a test read mode for the memory cell array.