Bus-Interleave Protocol for Multi-LUN Address Register Integrity
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Solution Overview
Problem
The sharing of a memory interface between multiple logic units (LUNs) in a flash memory chip leads to address register corruption due to mismatched addresses, particularly during multi-plane operations, affecting the efficiency and reliability of LUN operations.
Innovation Solution
Implementing a pending status for the first LUN to ignore non-multi-plane operation commands and protect the address register by only latching addresses corresponding to multi-plane program operations, using an address entry and address counter to manage command signals and enable latching only when a set of multi-plane operations is complete.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple LUNs share a memory interface, then device complexity is reduced and productivity is improved, but address register corruption occurs due to mismatched addresses
Solution Approach 1:
The patent applies preliminary action by setting a pending status flag before executing multi-plane program operations. This status is set in advance to indicate that the LUN is currently processing a multi-plane operation, which prevents address register corruption by blocking unrelated read operations from interrupting the sequence. The pending status is established before the actual operation begins, ensuring that address latching only occurs when appropriate.
Solution Approach 2:
The patent implements feedback through the pending status mechanism that provides continuous information about the current operation state. When a multi-plane program operation is detected, the pending status is activated and maintains this state throughout the operation sequence. This feedback loop allows the system to distinguish between valid address latching moments and inappropriate interruptions, ensuring reliable address register management while maintaining shared interface access.
2Productivity
If the first LUN receives read operation commands between multi-plane program operations, then the memory interface is utilized more efficiently, but address data in the address register becomes corrupted
Solution Approach 1:
The patent extracts the problematic read operation commands from the multi-plane program operation sequence by using the pending status flag. When pending status is active, the system identifies and separates out read operations that would cause address register corruption. These extracted read commands are either delayed until the multi-plane operation completes or are blocked entirely, preventing them from interfering with the address latching process while still allowing interface utilization during appropriate time windows.
Data Source
AI summary
A memory device includes a first logic unit (LUN) and a second LUN. The first LUN is coupled to the second LUN and configured to receive a first multi-plane operation command of a set of multi-plane operation commands corresponding to the first LUN, latch a first address of the first multi-plane operation command into a first address register of the first LUN, receive a single-plane operation command that includes a second address and corresponds to the second LUN, and keep latching the first address into the first address register.