Bi-directional Multi-drop Bus Memory Impedance Matching
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Solution Overview
Problem
Conventional memory systems employing stub series terminated logic (SSTL) face issues with signal integrity due to reflected waves caused by impedance mismatch, limiting bandwidth to less than 2 Gbps, and existing solutions like FB-DIMM and XDR introduce latency or reduce bandwidth as the number of modules increases.
Innovation Solution
A bi-directional multi-drop bus system is designed with serially coupled connectors and loads, where the first and second serial loads are determined by specific impedance equations, ensuring impedance matching at each transmission line terminal, thereby eliminating reflected waves and maintaining uniform voltage levels across memory modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If SSTL (stub series terminated logic) is employed in multi-drop bus systems, then bandwidth can be increased to 166-1600 Mbps, but reflected waves caused by impedance mismatch occur, causing inter-symbol interference (ISI) and limiting bandwidth to below 2 Gbps
Solution Approach 1:
The patent applies local quality by implementing different termination strategies at different locations along the bus. Specifically, each stub is equipped with a series resistor (Rser) having a specific impedance value that matches the characteristic impedance of the transmission line, while the main bus uses parallel termination resistors (Rpar). This localized impedance matching at each stub connection point eliminates reflected waves without requiring the entire bus to use a single termination method, thereby resolving the contradiction between achieving high bandwidth and maintaining signal integrity.
Solution Approach 2:
The patent employs parameter changes by carefully selecting and adjusting the impedance values of the series resistors (Rser) and parallel resistors (Rpar) to match the characteristic impedance of the transmission line. By changing the resistance parameters to specific values that satisfy impedance matching conditions, the system eliminates reflected waves and inter-symbol interference, enabling bandwidth expansion beyond the 2 Gbps limit while maintaining reliable signal transmission.
2Reliability
If FB-DIMM technique with advanced memory buffer (AMB) is used, then signal deterioration is compensated and reflected wave problems are solved, but latency is introduced to memory requests and additional power consumption occurs
Solution Approach 1:
The patent extracts and eliminates the root cause of signal deterioration - the reflected waves caused by impedance mismatch at stub connections - by implementing series resistors at each stub. This direct approach removes the harmful reflected waves before they can cause interference, rather than attempting to compensate for signal deterioration after it occurs. This eliminates the need for additional buffering components like AMB, thereby avoiding the latency and power consumption penalties associated with FB-DIMM techniques while still achieving reliable signal transmission.
3Quantity of substance
If more memory modules are connected to the multi-drop bus, then system capacity increases, but reflected wave interference worsens and bandwidth decreases
Solution Approach 1:
The patent applies local quality by equipping each stub connection to memory modules with a series resistor having impedance matching characteristics. This localized impedance matching at each connection point ensures that reflected waves are eliminated regardless of how many memory modules are connected to the bus. Consequently, the system can expand capacity by adding more memory modules without experiencing the bandwidth degradation that would normally result from increased reflected wave interference.
Data Source
AI summary
A bus system includes a plurality of stubs; a plurality of connectors, each of which is serially coupled between a corresponding one of the stubs and a corresponding one of memory modules; a plurality of first serial loads, each of which is serially coupled to a corresponding one of the connectors; and a plurality of second serial loads, each of which is serially coupled to characteristic impedance of a transmission line of a corresponding one of the stubs, wherein the first and the second serial loads are determined to be impedance matched at each transmission line terminal of the stubs.