Logic Circuit Coupling Arrangements TRIZ Cases
- Bi-directional Multi-drop Bus Memory Impedance Matching
Serial loads match impedance at each stub terminal, eliminating reflected waves and enabling 3.3 Gbps bandwidth without added latency.
- Bias Circuit for High-Voltage RF Switch Voltage Distribution
Position-dependent bias voltages counterbalance parasitic capacitances and leakage currents in stacked RF switches.
- On-Die Termination Control Using Latency Blocks for Impedance Matching
A latency block generates timing signals to adjust the active period of an ODT enable signal, resolving control difficulties at shorter clock frequencies.
- Decoupling Capacitor Relocation for SSD PHY Noise Reduction
Relocating a decoupling capacitor to the I/O edge reduces equivalent series resistance and noise in solid state drive controllers.
- T-Coil Network Bandwidth and ESD Immunity Design
A T-coil network design method adjusts parasitic bridge capacitance to optimize impedance matching.
- IC Layout Metal Cut Spacing Adjustment for DGE Suppression
Automated layout modification shifts device cells to maintain horizontal spacing between internal metal cuts.