Decoupling Capacitor Relocation for SSD PHY Noise Reduction

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Solution Overview

Problem

Conventional SSD controller designs face limitations due to the limited capacitance and high equivalent series resistance (ESR) of decoupling capacitance (decap) components, which are scattered throughout the physical layer (PHY) and occupy valuable IC area, leading to size and power usage issues.

Innovation Solution

The proposed solution involves positioning a decoupling capacitance component a non-zero distance away from the PHY core component, allowing for more efficient space usage, larger capacitance values, and lower ESR by relocating the decoupling core component to the edge of the logic circuit assembly, enabling direct wiring between the core logic and PHY, and using metal-oxide-metal (MOM) or MOS capacitors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If decap components are scattered throughout the PHY layer to minimize noise and voltage drops, then noise reduction is improved, but IC area usage deteriorates and ESR increases

Engineering Contradiction:
ImprovenoiseVSAvoidIC area
Core Design Contradiction:
Object-affected harmful factorsVSArea of stationary object

Solution Approach 1:

The patent extracts the decoupling capacitance function from the scattered decap components throughout the PHY layer and consolidates it into a single large-capacitance component located in the I/O component area. This extraction maintains the noise mitigation function while freeing up valuable IC area in the core logic and PHY regions.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent merges multiple small-capacitance decap cells distributed across the PHY layer into a single large-capacitance decoupling component. This consolidation achieves the same or better decoupling effect with lower ESR while occupying less total IC area, as the merged component can be positioned optimally in the I/O area with direct electrical coupling to the PHY core.

Inventive Principle:
Principle #5Merging (Combining)

2Object-affected harmful factors

If decap components are distributed throughout the design, then voltage drop mitigation is improved, but ESR increases due to physical distribution

Engineering Contradiction:
Improvevoltage dropsVSAvoidESR
Core Design Contradiction:
Object-affected harmful factorsVSReliability

Solution Approach 1:

The patent extracts the decoupling function from distributed small-capacitance cells and implements it through a single large-capacitance component with low ESR. This extracted implementation maintains effective voltage drop mitigation while achieving lower overall ESR because the large capacitor has inherently lower equivalent series resistance compared to multiple small capacitors in parallel.

Inventive Principle:
Principle #2Taking out (Extraction)

3Ease of manufacture

If standard decap components are used in PHY blocks, then integration is achieved, but size constraints and geometry limitations worsen

Engineering Contradiction:
ImproveintegrationVSAvoidcomponent size
Core Design Contradiction:
Ease of manufactureVSArea of moving object

Solution Approach 1:

The patent extracts the decoupling capacitance implementation from the constrained PHY block area and relocates it to the I/O component area. This extraction allows the use of larger-capacitance components without interfering with the size and geometry constraints of the PHY core, while still providing effective decoupling through direct electrical coupling.

Inventive Principle:
Principle #2Taking out (Extraction)

4Reliability

If decap components are placed close to PHY core, then decoupling effectiveness is improved, but valuable logic circuit area is consumed

Engineering Contradiction:
Improvedecoupling effectivenessVSAvoidlogic circuit area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent extracts the decoupling component from the core logic area and relocates it to the I/O component area, maintaining electrical coupling effectiveness while freeing up valuable logic circuit area for higher-priority components. The extraction leverages the electrical coupling path through the I/O interface to achieve decoupling without physical proximity to the PHY core.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS10545902B2Devices and methods for decoupling of physical layer
Publication Date: 2020.01.28 SANDISK TECHNOLOGIES LLC
  • US10545902B2 patent drawing
  • US10545902B2 patent drawing
  • US10545902B2 patent drawing

AI summary

A device with a physical layer (PHY) core component, a PHY I/O component, a decoupling I/O component, and a decoupling core component, where the PHY core component is adjacent to the PHY I/O component, the PHY I/O component is adjacent to the decoupling I/O component, the decoupling I/O component is adjacent to the decoupling core component and is positioned a first distance away from the PHY core component, and the decoupling core component is adjacent to an edge of the device and is positioned a second distance away from the PHY core component.