On-Die Termination Control Using Latency Blocks for Impedance Matching

The patent introduces a dynamic latency control mechanism that adjusts the active period of the ODT enable signal based on clock frequency. The latency block receives a latency control signal and dynamically modifies the timing characteristics of the ODT enable signal, allowing the system to adapt to different clock frequencies while maintaining accurate control of the active period.

The patent changes the timing parameters of the ODT enable signal by introducing a latency control mechanism. The latency block modifies the active period duration based on the latency control signal, which is generated in response to the clock frequency. This parameter adjustment allows accurate control even at shorter clock frequencies where conventional fixed-timing approaches fail.

The patent divides the ODT control function into separate modular blocks: an input buffer for signal conditioning, a latency block for timing adjustment, an enable signal generation block for active period control, and an ODT block for impedance control. This segmentation allows each block to perform its specific function independently, making the overall system more manageable and adaptable to different clock frequencies without excessive complexity.

The patent introduces a latency block as an intermediary component between the ODT control signal input and the enable signal generation. This intermediary block receives the latency control signal and translates it into appropriate timing adjustments for the ODT enable signal, providing flexible active period control while isolating the complexity within a dedicated module rather than distributing it throughout the entire control circuit.