C-Shaped Vertical Channel Structure With Spacers for Gate Isolation
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Solution Overview
Problem
Current semiconductor devices with vertical nanosheet or nanowire structures face challenges in controlling the thickness or diameter due to process fluctuations, and forming spacers on the sides of gate stacks in a vertical direction is difficult, limiting integration density and device performance.
Innovation Solution
A semiconductor device with a C-shaped nanosheet or nanowire channel portion and spacers is developed, featuring a method that includes patterning a stack of material layers, laterally recessing to form recess portions, and creating spacers between gate stacks and source/drain regions, which enhances electrical isolation and reduces parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional spacer formation process is used, then spacer can be formed on opposite sides of gate stack in lateral direction, but it is difficult to form spacer on opposite sides of gate stack in vertical direction
Solution Approach 1:
The patent inverts the conventional approach by forming spacers in the vertical direction rather than the lateral direction. The method uses lateral recessing to create vertical spacer regions, fundamentally changing the orientation of spacer formation to enable vertical device fabrication.
Solution Approach 2:
The patent transitions from two-dimensional lateral spacer formation to three-dimensional vertical spacer formation by using lateral recessing combined with vertical material deposition. This dimensional change enables spacer formation on the top and bottom surfaces of the gate stack.
2Device complexity
If vertical nanosheet or nanowire device is used, then device structure is achieved, but it is difficult to control thickness or diameter of nanosheet or nanowire due to process fluctuations
Solution Approach 1:
The patent performs preliminary lateral recessing to define the channel region boundaries before forming the nanosheet or nanowire. This pre-defined template guides subsequent material deposition, ensuring precise thickness and diameter control of the vertical channel structure.
Solution Approach 2:
The patent introduces position retaining layers as intermediary structures that temporarily hold the channel layer in place during processing. These layers act as placeholders that define the final position and dimensions of the nanosheet or nanowire, improving manufacturing precision.
3Productivity
If integration density is increased, then device performance is enhanced, but device structure limitation prevents further improvement
Solution Approach 1:
The patent utilizes the vertical dimension for spacer formation and channel structure, freeing up lateral space for higher integration density. By moving spacer formation to the vertical domain, more devices can be packed horizontally on the substrate.
Solution Approach 2:
The patent segments the device into distinct vertical layers including position retaining layers, channel layers, and spacer regions. This segmentation allows independent optimization of each layer for its specific function, enabling higher overall integration density.
Data Source
AI summary
Disclosed are a semiconductor device with a spacer and a C-shaped channel portion, a method of manufacturing the same, and an electronic apparatus including the semiconductor device. The semiconductor device may include: a channel portion on a substrate, wherein the channel portion includes a curved nanosheet or nanowire with a C-shaped cross-section; a first source/drain portion and a second source/drain portion respectively located at upper and lower ends of the channel portion with respect to the substrate; a first gate stack and a second gate stack located on opposite sides of the channel portion; a first spacer located between the first gate stack and the first source/drain portion and between the first gate stack and the second source/drain portion respectively; and a second spacer located between the second gate stack and the first source/drain portion and between the second gate stack and the second source/drain portion respectively.