Nanoinformatics TRIZ Cases

Work-function silicide on dual-side source/drain contacts lowers Schottky barriers and cuts contact resistance in scaled semiconductor fins.

A gate separation liner and filling film improve insulation between closely spaced gates, helping dense transistors maintain stable operation.

Air-gap and porous dielectric spacers improve gate-channel coupling while cutting capacitance, OFF-state current, and short-channel effects.

A strain-compensated InGaAs/GaAsSb superlattice on InP extends SWIR cutoff beyond 2μm while improving quantum efficiency at non-cryogenic temperatures.

An insulating layer separates the channel from source/drain regions to suppress Fermi-level pinning and improve electrostatic control.

A single grating forms gate and trench contact cuts, simplifying nanowire transistor fabrication while preserving tight spacing and reducing variation.

A defect modification layer and thin relaxed SiGe buffer enable defect-free germanium GAA nanowires without long processing or wafer bow.

Mixed nanowire and nanosheet GAA SRAM macros balance low leakage and fast writes while avoiding write assist circuitry.

Spacer and filling patterns define precise dielectric grooves for wiring lines, improving dense MOSFET interconnect spacing and connection reliability.

Stacked superlattice monolayers in GAA nanostructures lower carrier effective mass, limit dopant diffusion, and improve mobility.

An air gap replaces dummy front-side S/D contact material to cut gate coupling capacitance and improve backside power rail performance.

Sealed air-gap low-k spacers between GAA gates and source/drain epitaxy reduce parasitic capacitance while maintaining electrical isolation.

A widened middle contact plug section increases epitaxial contact area in stacked nanowire FETs, easing small-opening limits and lowering resistance.

Stacked wiring layers connect transistor contacts across standard cells to cut resistance and support faster, denser IC layouts.

Reversed source-drain placement in paired TFETs eases CMOS integration while preserving low-power switching and a steep sub-threshold slope.

Pre-trimmed channel members and wider inner spacers enlarge junction overlap in multi-gate transistors, cutting parasitic resistance and threshold rise.

Nitrogen-rich inner spacer surfaces improve selective source/drain epitaxy in nanosheet FETs, reducing random nucleation, defects, and voids.

A flowable CVD sacrificial layer blocks work function metal between p-type nanostructures, improving threshold control and gap fill.

A stepped gate spacer widens upper spacer gaps to improve etchant penetration, reduce defects, and lower parasitic capacitance in dense devices.

An etch-resistant insulative layer and polymer coating let graphene stay clean and stable while the silicon support wafer is thinned or removed.

A trap-rich layer with nano-dots or a doped negative charge layer neutralizes fixed positive charges to block parasitic surface conduction.

A monolithic stacked NSHFET-FinFET process uses opposite-side gate formation and self-aligned channels to improve geometry flexibility and alignment.

A protective dielectric shields the top GAA channel during dummy gate etching and helps keep metal gate profiles and threshold voltage uniform.

Narrowed hybrid-fin centers open gate-fill space around nanowires, reducing resistance and improving yield in dense GAA transistor fabrication.

Germanium concentration gradients and a preformed silicon side layer protect FinFET channel and source/drain regions during fine-pattern manufacturing.

Double-side silicide contacts with integral vias boost 3DIC connectivity, enable backside links, and reduce IC thickness without TSV overhead.

Reduced-pressure CVD and annealing form a uniform sub-1 nm Ge cladding on silicon channels while avoiding island formation in scaled nanosheet and finFET structures.

A graded SiGe stack balances etching selectivity and silicon loss, enabling cleaner SiGe removal and reduced inter-diffusion in GAA fabrication.

A sacrificial dummy layer creates an air gap beside source/drain contacts, easing overlay limits and lowering parasitic capacitance in scaled layouts.

Hydrogen radical treatment and selective dry etching remove oxygen impurities to shape GAA nanosheets and inner spacers with better mobility.

Forming semiconductor material in a contact trench and converting it to silicide lowers source/drain contact resistance and eases scaled interconnect fabrication.

Vertical spacer formation around a C-shaped nanosheet or nanowire improves gate isolation, channel control, and parasitic capacitance reduction.

A channel that wraps around a metal contact cuts resistance in ultra-thin 2D VFETs, enabling more reliable vertical source and drain connections.

Thermal treatment or an opposite-stress mask layer reduces hard mask distortion, preserving sub-micron pattern fidelity during lithography.

Complete dummy gate removal and trench isolation in stacked GAA nanostructures reduce leakage while improving process window and yield.

Bismuth deposited on 2D semiconductors lowers the contact barrier, enabling ohmic interfaces with ultra-low resistance and strong current injection.

Selective trench CD shrink creates recessed source/drain contacts that keep large contact area while lowering gate parasitic capacitance.

A hat-shaped inner spacer leaves nanowire edge surfaces exposed, enabling low-resistance source/drain junctions with strong gate control.

An undoped semiconductor, silicon-rich dielectric, and air spacer isolate GAA FET S/D regions to curb leakage and short channel effects.

Sequential doped regions inside an FET enable passive devices or BJTs before substrate thinning, preserving BSPDN integration and device density.

Separating the upper nanowire under gate spacers reduces parasitic capacitance while preserving conduction and improving AC behavior.

Stacked silicon and oxygen monolayers raise carrier mobility while a cap layer blocks diffusion and preserves enriched 28Si epitaxy.

Layer-by-layer oxygen treatment raises interfacial oxygen in p-type gate work function stacks, boosting effective work function and lowering threshold voltage.

Insulator regions beneath source and drain block subfin leakage in non-planar transistors while preserving charge carrier control.

Oxygen- and fluorine-resistant capping layers protect work function metals, enabling reliable threshold voltage tuning in scaled multi-gate transistors.

Sidewall metallization adds frontside and backside source/drain contact area, easing scaling limits and improving backside power delivery.

SiGe etch stop layers enable multi-step trench etching with uniform depth and geometry, improving transistor isolation and reducing leakage.

Bridge portions connect adjacent gate lines to prevent collapse during nanosheet transistor fabrication while enabling higher device density.

Nitrogen-doped upper channel regions and silicon oxynitride patterns preserve gate-to-source/drain insulation during etching and cleaning.

Selective removal of sacrificial layers enables GAA and FinFET fabrication on one substrate with simpler processing, lower cost, and higher yield.