Dog-Bone Channel Structure for Low-Resistance Multi-Gate Transistors
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Solution Overview
Problem
Existing multi-gate devices, such as MBC transistors, face challenges with increased parasitic resistance and junction resistance due to the formation of inner spacer features, leading to reduced on-state current and increased threshold voltage, as the scaling down process results in etching of channel layers and reduced junction overlap areas.
Innovation Solution
The method involves forming a stack with channel layers thicker than sacrificial layers, selectively removing sacrificial layers to release channel members, and trimming them to increase channel-channel spacing, while forming wider inner spacers along the gate length direction to prevent damage to source/drain features, resulting in a dog-bone shape of channel members with an enlarged junction overlap area, thereby reducing junction resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If inner spacer features are formed by recessing sacrificial layers, then gate structure is spaced away from source/drain features, but channel layers are lost leading to reduced junction overlap area and increased parasitic resistance
Solution Approach 1:
The patent performs preliminary trimming of channel layers before forming inner spacers to prevent excessive loss of channel layers during the spacer formation process. This preliminary action ensures that sufficient channel layer remains to maintain adequate junction overlap area while still achieving the desired gate spacing.
Solution Approach 2:
The patent optimizes the depth and dimensions of inner spacer recesses to control the amount of channel layer loss. By carefully adjusting the recess parameters, the patent achieves a balance between providing adequate gate spacing and preserving sufficient junction overlap area to maintain low parasitic resistance.
2Reliability
If conventional inner spacer formation is used, then gate control is improved, but junction overlap area is reduced leading to increased threshold voltage
Solution Approach 1:
The patent performs preliminary trimming of channel layers to establish optimal dimensions before inner spacer formation. This ensures that even after spacer formation reduces the junction overlap area, sufficient channel layer remains to maintain appropriate threshold voltage while still achieving improved gate control.
Solution Approach 2:
The patent applies different treatments to different regions of the channel layer. The channel layers are trimmed to specific dimensions in regions where junction overlap is critical, while allowing other regions to maintain dimensions optimized for gate control, creating locally optimized structures.
Data Source
AI summary
A semiconductor device according to the present disclosure includes a channel member including a first connection portion, a second connection portion and a channel portion disposed between the first connection portion and the second connection portion, a first inner spacer feature disposed over and in contact with the first connection portion, a second inner spacer feature disposed under and in contact with the first connection portion, and a gate structure wrapping around the channel portion of the channel member. A shape of a cross-sectional view of the channel member includes a dog-bone shape. By providing the dog-bone shape channel member, a parasitic resistance of the semiconductor device is advantageously reduced, and performance of the semiconductor device may be significantly improved.