Complementary TFET Switch Layout for Easier CMOS Integration
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Solution Overview
Problem
Integrating tunnel field-effect transistors (TFETs) into complementary switch devices is challenging due to their asymmetrical source and drain regions, which differ from the symmetrical regions of traditional MOSFETs.
Innovation Solution
A complementary switch device configuration using a first and second tunnel field-effect transistor with III-V group compound semiconductor nanowires on a IV group semiconductor substrate, where the positional relationship between the source and drain electrodes is reversed in each transistor, allowing for easy integration by maintaining a similar configuration across both transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If TFETs are integrated into complementary switch devices, then power consumption is reduced and sub-threshold slope is improved (40 mV/digit or smaller), but integration difficulty increases due to asymmetrical source and drain regions
Solution Approach 1:
The patent applies asymmetry principle by intentionally designing the TFET structure with distinct source and drain regions having different doping types (n-type and p-type respectively). This asymmetrical configuration enables the tunneling mechanism that achieves sub-60mV/digit sub-threshold slope and low power consumption, while the patent resolves the integration difficulty by providing specific structural arrangements including III-V group compound semiconductor nanowires on IV group semiconductor substrates with carefully engineered doping profiles
Solution Approach 2:
The patent employs parameter changes by modifying the doping concentration profiles in the source and drain regions, using different semiconductor materials (III-V group compound semiconductors like InGaAs on Si substrates), and adjusting the gate electrode configurations to achieve optimal tunneling characteristics. These parameter adjustments enable the TFET to achieve 40 mV/digit or smaller sub-threshold slope while maintaining manufacturability through controlled fabrication processes
2Reliability
If the sub-threshold slope is reduced below 60 mV/digit using tunneling mechanism, then switching characteristics are improved, but device complexity increases due to asymmetrical source and drain regions
Solution Approach 1:
The patent utilizes asymmetry by creating TFETs with n-type and p-type doped regions in specific configurations that enable band-to-band tunneling. The asymmetrical doping profile (with one heavily doped region and one lightly doped region) is essential for achieving sub-60mV/digit sub-threshold slope, as it creates the necessary electric field distribution for efficient carrier tunneling while maintaining device reliability
Solution Approach 2:
The patent employs composite materials by combining III-V group compound semiconductors (such as InGaAs, InP) with IV group semiconductor substrates (such as Si, Ge). This material combination enables the tunneling mechanism to achieve superior switching characteristics with 40 mV/digit or smaller sub-threshold slope, while the heterostructure provides a framework that manages the complexity through well-defined material interfaces and growth processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables the easy integration of TFETs into semiconductor microprocessors and highly integrated circuits, reducing power consumption and achieving a sub-threshold slope of 40 mV/digit or smaller, facilitating low-power operation.
Implementation Method 1
a gate electrode configured to apply an electric field to an interface between the (111) surface and the first region
Implementation Method 2
Tunneling FETs (hereinafter referred to as "TFETs") have been reported as switch devices that exceed this physical theoretical limit and operate with a smaller subthreshold
Data Source
AI summary
This complementary switch element includes: a first TFET having a first conductive channel; and a second TFET having a second conductive channel. Each of the first TFET and the second TFET includes: a group IV semiconductor substrate doped in a first conductive type; a nanowire which is formed of a group III-V compound semiconductor and is disposed on the group IV semiconductor substrate; a first electrode connected to the group IV semiconductor substrate; a second electrode connected to the nanowire; and a gate electrode. The nanowire includes a first area connected to the group IV semiconductor substrate and a second area doped in a second conductive type. In the first TFET, the second electrode is a source electrode, and the first electrode is a drain electrode. In the second TFET, the first electrode is a source electrode, and the second electrode is a drain electrode.