Stacked Nanostructure Gate Isolation for Leakage-Controlled GAA
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving efficient three-dimensional designs for higher device density and performance, particularly in the fabrication and design aspects as the industry transitions to nanometer technology process nodes.
Innovation Solution
The development of a gate all around (GAA) transistor structure is achieved by forming alternately stacked first and second semiconductor layers over a substrate, patterning them to create fin structures, and then forming gate structures within trenches, with an isolation sealing layer to separate the gates, allowing for increased process window and improved yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional planar transistor designs are used, then fabrication processes are simpler, but device density and performance are limited
Solution Approach 1:
The patent transitions from traditional planar (2D) transistor designs to three-dimensional vertically stacked transistor structures. Multiple active regions are stacked vertically over a common trench, enabling increased device density by utilizing the vertical dimension rather than only lateral expansion.
Solution Approach 2:
The transistor structure is segmented into multiple discrete active regions stacked vertically, with each active region having its own gate electrode. This segmentation allows independent control of each stack while achieving high density through vertical arrangement.
2Productivity
If three-dimensional vertically stacked transistor structures are implemented, then device density increases, but fabrication process complexity and difficulty increase
Solution Approach 1:
A common trench structure is formed first as a preliminary step, providing a predefined template for subsequent vertical stacking of active regions. This preliminary trench formation simplifies the overall fabrication process by establishing the basic architecture before adding complex vertical structures.
Solution Approach 2:
Dielectric materials are used as intermediary layers between stacked active regions and around gate electrodes. These intermediary dielectric layers provide electrical isolation and structural support, enabling the complex vertical stacking to be manufactured with standard fabrication techniques.
3Ease of manufacture
If dummy gate structures are retained in trench regions, then process simplicity is maintained, but leakage current increases and yield decreases
Solution Approach 1:
Dummy gate structures are completely removed from trench regions where they would create leakage paths. This extraction eliminates the source of leakage current and associated reliability issues, with the trench subsequently filled with dielectric material to maintain structural integrity.
Solution Approach 2:
The potential harm of having dummy gates (which simplify processing but cause leakage) is converted into a benefit by intentionally removing them and using the resulting trenches for beneficial purposes: improving device isolation, enabling better electrical control, and increasing overall device yield through reduced leakage current.
4Reliability
If complete dummy gate removal and trench formation is performed, then leakage current is reduced and yield improves, but fabrication process complexity increases
Solution Approach 1:
The removal of dummy gates and the formation of trenches for vertical stacking are merged into a unified fabrication approach. The same trench structures that would have contained dummy gates are instead used to house vertically stacked active regions, combining what would be separate complex processes into one integrated methodology.
Data Source
AI summary
A semiconductor device structure is provided. The semiconductor device structure includes a first stacked nanostructure and a second stacked nanostructure formed over a substrate. The semiconductor device structure includes a first gate structure formed over the first stacked nanostructure, and the first gate structure includes a first portion of a gate dielectric layer and a first portion of a filling layer. The semiconductor device structure includes a second gate structure formed over the second stacked nanostructure, and the second gate structure includes a second portion of the gate dielectric layer and a second portion of the filling layer. The semiconductor device structure includes a first isolation layer between the first gate structure and the second gate structure, wherein the first isolation layer has an extending portion which is formed in a recess between the gate dielectric layer and the filling layer.