Uniform Grid Metal Gate and Trench Contact Cut for Scaled Nanowires
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Solution Overview
Problem
The scaling of multi-gate and nanowire transistors poses challenges in maintaining mobility and short channel control as device dimensions approach the 10 nanometer node, with constraints on lithographic processes leading to trade-offs between feature dimension and spacing, and complex processing schemes for trench contact and metal gate plug removal are costly and introduce variation.
Innovation Solution
The implementation of a method for fabricating integrated circuit structures with a uniform grid metal gate and trench contact cut, using a single 'infinite' grating to generate trench contact and gate cut plugs, followed by local plug removal to reconnect cut gate and contact portions, and the use of angled plasma etching to remove metal gate cut plugs without impacting grating height or critical dimension, thereby simplifying the process and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional processes are used for trench contact and metal gate plug removal, then device fabrication can proceed, but the process becomes complex and costly with introduced variation
Solution Approach 1:
The patent combines the trench contact formation and metal gate plug removal operations into a single integrated process flow. The gate cut plugs are formed simultaneously with trench contact plugs using the same lithographic grating, and both are removed together through a unified etch process, eliminating the need for separate processing steps and reducing overall process complexity and variation
Solution Approach 2:
The patent employs a single 'infinite' grating structure that serves multiple functions: it defines both the trench contact locations and the metal gate cut positions. This universal patterning approach allows one lithographic element to perform what would traditionally require multiple separate patterning operations, simplifying the manufacturing process
2Productivity
If feature dimensions are scaled down to maintain increased device density, then more devices can be fabricated per chip, but lithographic constraints create trade-offs between critical dimension and spacing
Solution Approach 1:
The patent transitions from conventional two-dimensional planar patterning to three-dimensional vertical structuring. By forming gate-all-around devices with vertical channels and surrounding gates, the design moves into the third dimension, allowing increased device density without proportionally increasing lithographic complexity. The single grating patterns features that will be vertically developed into 3D structures
3Manufacturing precision
If metal gate cut plugs are removed using conventional etching, then plugs can be removed, but grating height and critical dimension are impacted
Solution Approach 1:
The patent introduces an intermediary sacrificial layer between the metal gate cut plugs and the underlying grating structure. This sacrificial layer protects the grating during the plug removal etch process, allowing complete plug removal without damaging the grating's critical dimensions. The sacrificial layer is selectively removed after plug removal, leaving the grating intact
Solution Approach 2:
The patent applies a protective coating or sacrificial layer to the grating structure before performing the metal gate cut plug removal etch. This preliminary protective action prevents the etch from affecting the grating height or critical dimensions, allowing aggressive plug removal chemistry to be used without compromising grating integrity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances process robustness, reduces costs, and improves device performance by allowing for seamless work function metal deposition and void-free metal fill, while maintaining tight endcap spacing and reducing cell height in scaled technology nodes.
Implementation Method 1
angled plasma etching to remove metal gate cut plugs
Data Source
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AI summary
Integrated circuit structures having uniform grid metal gate and trench contact cut, and methods of fabricating integrated circuit structures having uniform grid metal gate and trench contact cut, are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires. A gate electrode is over the vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. A first dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. A second dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the second dielectric cut plug structure laterally spaced apart from and parallel with the first dielectric cut plug structure.