FET Structure With Integrated Passive Devices for BSPDN Layout

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Solution Overview

Problem

The challenge in forming passive devices such as resistors or diodes within field-effect transistor (FET) structures, like FinFETs or nanosheet transistors, is exacerbated by the backside power distribution network (BSPDN) formation process, which complicates the integration of these devices due to substrate thinning requirements.

Innovation Solution

A field-effect transistor structure is developed with sequentially connected doped regions forming a passive device or bipolar junction transistor (BJT), including a substrate with specific doped regions and channel structures, along with an isolation layer and backside contact plugs, allowing for the formation of BSPDN structures that facilitate the integration of passive devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If substrate thinning process is applied to form BSPDN, then routing complexity at BEOL is reduced, but ability to form passive devices in substrate is compromised

Engineering Contradiction:
Improverouting complexityVSAvoidability to form passive devices
Core Design Contradiction:
Device complexityVSEase of manufacture

Solution Approach 1:

The substrate functionality is segmented into two parts: power distribution (BSPDN) handled at the backside through thinning, and passive device formation (resistors, diodes, BJTs) handled in the bulk substrate before thinning. This segmentation allows both functions to coexist without interference.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Passive devices are formed in the substrate before the thinning process is applied. By performing the passive device formation in advance, the substrate retains sufficient thickness to accommodate these devices, while subsequent thinning enables BSPDN formation at the backside.

Inventive Principle:
Principle #10Preliminary action

2Volume of stationary object

If substrate is thinned for BSPDN formation, then space for BSPDN is created, but device density integration is reduced

Engineering Contradiction:
Improvespace for BSPDNVSAvoiddevice density
Core Design Contradiction:
Volume of stationary objectVSProductivity

Solution Approach 1:

The solution moves passive devices from the traditional planar layout to a vertical configuration within the substrate depth. Multiple doped regions are stacked sequentially in the vertical dimension, enabling high-density integration while preserving substrate thickness for BSPDN formation.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Adaptability or versatility

If passive devices are formed in substrate, then device functionality is enhanced, but manufacturing process complexity increases

Engineering Contradiction:
Improvedevice functionalityVSAvoidmanufacturing process complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The formation of passive devices is merged with the existing FET manufacturing process sequence. Doped regions for passive devices are created using the same ion implantation and thermal processing steps already required for FET source/drain formation, eliminating the need for separate passive device fabrication streams.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the efficient integration of passive devices and BJTs within FET structures, improving device density and performance by simplifying the manufacturing process and maintaining the integrity of the substrate for BSPDN formation.

Implementation Method 1

doping at least one 1st doped region in the substrate with a first dopant to form a first modified region having a first modified electrical conductivity

Methodology Applied
Scientific EffectDoping: Dopants

Implementation Method 2

an isolation layer on a bottom surface of the substrate

Methodology Applied
Scientific EffectElectrical insulation: Dielectric

Data Source

PatentEP4333061A1Field-effect transistor structure including passive component or bipolar junction transistor with back side power distribution network (BSPDN)
Publication Date: 2024.03.06 SAMSUNG ELECTRONICS CO LTD
  • EP4333061A1 patent drawingFigure 1A
  • EP4333061A1 patent drawingFigure 1B
  • EP4333061A1 patent drawingFigure 2

AI summary

Provided is field-effect transistor structure including: a substrate (105) including therein at least one 1st doped region (N1), a 2nd doped region (N2) on one side of the 1st doped region, and a 3rd doped region (N3) on another side of the 1st doped region; a 1st channel structure including therein a 4th doped region (N4) on the 2nd doped region (N2) in the substrate; and a 2nd channel structure (110), at a side of the 1st channel structure, including therein a 5th doped region (N5) on the 3rd doped region (N3) in the substrate, wherein the 4th, 2nd, 1st, 3rd and 5th doped regions form a sequentially connected passive device.