Stepped Gate Spacer Profile for Dense FinFET Etching
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Solution Overview
Problem
Current methods for forming gate spacers at reduced length scales in semiconductor devices are inadequate, leading to structural defects and compromised device performance due to reduced spacings between gate spacers, which result in under-etching of source/drain recesses, limited material removal during epitaxial growth, and inadequate etchant penetration.
Innovation Solution
A method is introduced where the thickness of gate spacers is adjusted along their height, with a sacrificial layer masking the bottom portion and selectively etching the top portion to widen the spacing between adjacent spacers, allowing for adequate etchant penetration and reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If gate spacing is reduced to increase device density, then functional density is improved, but structural defects occur and device performance is compromised
Solution Approach 1:
The gate spacer is designed with non-uniform thickness, having a first thickness at the bottom portion and a second thickness at the top portion, where the second thickness is greater than the first thickness. This local variation in geometry allows the spacer to provide adequate spacing for etchant penetration at the top while maintaining proper alignment at the bottom, thus resolving the contradiction between reduced gate spacing for density and adequate spacing for reliable processing
Solution Approach 2:
The invention introduces a vertical dimension variation in the gate spacer thickness, transitioning from a uniform 2D geometry to a 3D graded geometry. This dimensional change enables the spacer to simultaneously satisfy conflicting requirements: maintaining narrow overall gate spacing for high device density while providing localized increased thickness at the top to ensure adequate etchant penetration and prevent structural defects
2Quantity of substance
If gate spacer thickness is reduced to increase device density, then functional density is improved, but etchant penetration becomes inadequate
Solution Approach 1:
The gate spacer features different thicknesses at different vertical locations: a first thickness at the bottom portion and a second greater thickness at the top portion. This local quality variation ensures that the top portion provides sufficient spacing for complete etchant penetration and proper source/drain recess formation, while the overall reduced spacing maintains high device density
Solution Approach 2:
The gate spacer is formed with a pre-designed non-uniform thickness profile before the source/drain recess etching process. This preliminary geometric configuration ensures that adequate spacing is already in place to allow etchant penetration, preventing under-etching defects and ensuring manufacturing precision in subsequent processing steps
3Ease of manufacture
If gate spacer thickness is uniform, then manufacturing is simplified, but parasitic capacitance increases and device performance decreases
Solution Approach 1:
The gate spacer is designed with non-uniform thickness, having a first thickness at the bottom portion and a second thickness at the top portion that is greater than the first thickness. This local variation optimizes the spacer to reduce parasitic capacitance between the gate and source/drain regions while maintaining adequate spacing for proper etching, thus improving device performance without significantly complicating the manufacturing process
Data Source
AI summary
A method of forming a semiconductor structure includes forming a semiconductor fin over a substrate, forming a dummy gate stack over the semiconductor fin, depositing a dielectric layer over the dummy gate stack, and selectively etching the dielectric layer, such that a top portion and a bottom portion of the dielectric layer form a step profile. The method further includes removing portions of the dielectric layer to form a gate spacer and subsequently forming a source/drain feature in the semiconductor fin adjacent to the gate spacer.