Semiconductor Structure with Graded SiGe Stack for Selective Etching

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Solution Overview

Problem

In semiconductor manufacturing, the etching process for gate-all-around transistor structures composed of Si and SiGe stacks faces challenges with inter-diffusion issues, where high germanium concentration leads to material loss in silicon layers and low germanium concentration results in ineffective etching selectivity, making it difficult to remove the SiGe layer effectively.

Innovation Solution

A SiGe stack with varying germanium concentrations is used, where a higher germanium concentration is placed in the middle and lower concentrations are at the interfaces with silicon layers, allowing for controlled etching rates to facilitate the removal of the SiGe layer while minimizing material loss, by employing a method that includes forming a first silicon germanium layer with a lower germanium concentration, a second with a higher concentration, and a third with an intermediate concentration, and adjusting their thicknesses to optimize etching performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If high germanium concentration is used in SiGe layer, then etching selectivity is improved, but material loss in silicon layer increases

Engineering Contradiction:
Improveetching selectivityVSAvoidmaterial loss in silicon layer
Core Design Contradiction:
Manufacturing precisionVSLoss of substance

Solution Approach 1:

The patent applies local quality by creating a SiGe stack with non-uniform germanium concentration distribution. The intermediate SiGe layer has higher germanium concentration (30-60%) to provide etching selectivity, while the first and third SiGe layers have lower germanium concentration (5-20%) to minimize inter-diffusion and material loss to adjacent silicon layers. This spatial variation in composition resolves the contradiction between achieving etching selectivity and preventing material loss.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent uses composite materials by constructing a multi-layer SiGe stack where each layer has different germanium concentration. This composite structure combines the benefits of high germanium concentration (etching selectivity) and low germanium concentration (reduced inter-diffusion) within a single integrated structure, allowing both requirements to be satisfied simultaneously.

Inventive Principle:
Principle #40Composite materials

2Loss of substance

If low germanium concentration is used in SiGe layer, then material loss in silicon layer is reduced, but etching selectivity deteriorates

Engineering Contradiction:
Improvematerial loss in silicon layerVSAvoidetching selectivity
Core Design Contradiction:
Loss of substanceVSManufacturing precision

Solution Approach 1:

The patent applies local quality by creating a SiGe stack with non-uniform germanium concentration distribution. The intermediate SiGe layer has higher germanium concentration (30-60%) to provide etching selectivity, while the first and third SiGe layers have lower germanium concentration (5-20%) to minimize inter-diffusion and material loss to adjacent silicon layers. This spatial variation in composition resolves the contradiction between achieving etching selectivity and preventing material loss.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent uses composite materials by constructing a multi-layer SiGe stack where each layer has different germanium concentration. This composite structure combines the benefits of high germanium concentration (etching selectivity) and low germanium concentration (reduced inter-diffusion) within a single integrated structure, allowing both requirements to be satisfied simultaneously.

Inventive Principle:
Principle #40Composite materials

3Device complexity

If single-layer SiGe structure is used, then device complexity is reduced, but ability to control etching rate distribution deteriorates

Engineering Contradiction:
ImproveSiGe structure complexityVSAvoidetching rate control capability
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent applies segmentation by dividing the SiGe layer into multiple sub-layers (first, second, and third SiGe layers) with different germanium concentrations. This segmentation allows independent optimization of each layer's properties: the intermediate layer provides etching selectivity while the outer layers minimize inter-diffusion, achieving better etching rate control than a single-layer structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent uses composite materials by constructing a multi-layer SiGe stack where each layer has different germanium concentration. This composite structure combines the benefits of high germanium concentration (etching selectivity) and low germanium concentration (reduced inter-diffusion) within a single integrated structure, allowing both requirements to be satisfied simultaneously.

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables effective removal of the SiGe layer with reduced material loss to the silicon layer, improving etching selectivity and facilitating subsequent operations by creating a necking structure in the etched profile that alleviates inter-diffusion issues and supports the formation of semiconductor structures.

Implementation Method 1

high germanium concentration leads to material loss in silicon layers and low germanium concentration results in ineffective etching selectivity

Methodology Applied
Scientific EffectEtching selectivity:

Implementation Method 2

inter-diffusion issues, where high germanium concentration leads to material loss in silicon layers

Methodology Applied
Scientific EffectInter-diffusion: Diffusion

Data Source

PatentUS11942513B2Semiconductor structure and method of fabricating the semiconductor structure
Publication Date: 2024.03.26 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11942513B2 patent drawing
  • US11942513B2 patent drawing
  • US11942513B2 patent drawing

AI summary

The present disclosure provides a semiconductor structure, including a substrate having a front surface, a first semiconductor layer proximal to the front surface, a second semiconductor layer over the first semiconductor layer, a gate having a portion between the first semiconductor layer and the second semiconductor layer, a spacer between the first semiconductor layer and the second semiconductor layer, contacting the gate, and a source/drain (S/D) region, wherein the S/D region is in direct contact with a bottom surface of the second semiconductor layer, and the spacer has an upper surface interfacing with the second semiconductor layer, the upper surface including a first section proximal to the S/D region, a second section proximal to the gate, and a third section between the first section and the second section.