Wiring Groove Patterning With Spacers for Dense MOSFET Interconnects
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Solution Overview
Problem
As semiconductor devices are scaled down, the operating characteristics of MOSFETs deteriorate, requiring methods to improve performance while addressing integration issues in fabricating semiconductor devices with superior performance.
Innovation Solution
A method involving the sequential formation of interlayer dielectric and mask layers, followed by the creation of spacer and filling patterns to form grooves in the dielectric layer for wiring line formation, using atomic layer deposition to ensure precise spacing and reduce process variance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MOSFET sizes are scaled down to increase integration, then device density improves, but operating characteristics deteriorate
Solution Approach 1:
The patent divides the mask pattern formation into multiple stages using different mask layers (upper mask layer and lower mask layer) with distinct patterns. The upper mask layer defines first spaces between protruding parts, while the lower mask layer defines second spaces between line parts, allowing independent optimization of spacing for electrical performance while maintaining high integration density.
Solution Approach 2:
The patent applies different spacing configurations in different regions: first spaces are formed between protruding parts of adjacent upper mask patterns, while second spaces are formed between line parts of lower mask patterns. This local differentiation allows optimization of electrical characteristics in specific areas without compromising overall device integration.
2Manufacturing precision
If complex multi-step patterning is used to improve wiring precision, then manufacturing precision improves, but process complexity increases
Solution Approach 1:
The patent combines the formation of first spaces and second spaces into a single etching process step. The spacer layer is formed to cover both upper and lower mask patterns simultaneously, and a single etching operation creates both types of spaces through the interlayer dielectric layer, reducing the number of separate process steps while maintaining high precision.
Solution Approach 2:
The patent introduces a spacer layer as an intermediary element that bridges the upper and lower mask patterns. This spacer layer serves as a unified etching mask that enables simultaneous formation of multiple space types, simplifying the process while ensuring precise spacing through the spacer's controlled thickness.
3Ease of manufacture
If traditional etching mask methods are used, then process simplicity is maintained, but wiring line connection reliability decreases
Solution Approach 1:
The patent performs preliminary formation of spacer layers and filling patterns before the actual etching of wiring grooves. The spacer layer is deposited and patterned in advance to define precise spacing, and the filling pattern is formed to ensure proper etch selectivity. These preliminary actions ensure reliable wiring line spacing and connection while maintaining process simplicity through a systematic sequence.
Solution Approach 2:
The spacer layer automatically defines the spacing between wiring lines through its conformal deposition on the mask patterns. The etching process self-aligns to the spacer edges, eliminating the need for additional alignment steps and ensuring consistent spacing without increasing process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances electrical characteristics by ensuring accurate spacing of wiring lines and simplifying the fabrication process, reducing the risk of line connection or disconnection, and improving overall device performance.
Implementation Method 1
using atomic layer deposition to ensure precise spacing and reduce process variance
Data Source
AI summary
Disclosed is a semiconductor device fabrication method including forming an interlayer dielectric layer and a lower mask layer on a substrate, forming on the lower mask layer first and second upper mask patterns spaced apart from each other in a first direction, wherein each of the first and second upper mask patterns has a line part extending in a second direction and a first protruding part protruding from the line part, forming a spacer covering sidewalls of the line parts of the first and second upper mask patterns and a filling pattern filling a space between the first protruding parts of the first and second upper mask patterns, etching the lower mask layer to form lower mask patterns, etching the interlayer dielectric layer to form grooves on the interlayer dielectric layer, and forming wiring lines in the grooves.