Fin-Base Isolation Structure for Leakage Control in GAA FETs
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Solution Overview
Problem
Current semiconductor manufacturing processes face challenges in preventing current leakage between adjacent source/drain (S/D) regions on the same fin base in gate-all-around (GAA) FETs due to the growth of epitaxial S/D regions on the fin bases, leading to short channel effects and increased complexity.
Innovation Solution
The formation of isolation structures between epitaxial S/D regions and fin bases, comprising an undoped semiconductor layer, a silicon-rich dielectric layer, and an air spacer, which electrically isolates the S/D regions from the fin bases, preventing current leakage and minimizing short channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If epitaxial S/D regions are grown on fin bases to increase storage capacity and processing speed, then device performance is improved, but current leakage between adjacent S/D regions occurs leading to short channel effects
Solution Approach 1:
The fin base is segmented into multiple isolated regions by introducing isolation structures between adjacent S/D regions. These isolation structures divide the continuous fin base into separate segments, preventing current leakage while maintaining the high-density configuration needed for improved device performance.
Solution Approach 2:
Isolation structures are introduced as intermediary elements between adjacent S/D regions on the fin base. These intermediary structures act as barriers that block current leakage paths while allowing the S/D regions to maintain their epitaxial growth on the fin base, thus preventing short channel effects without sacrificing device performance.
2Object-generated harmful factors
If isolation structures are introduced to prevent current leakage, then short channel effects are minimized, but manufacturing process complexity increases
Solution Approach 1:
The isolation structures are formed preliminarily during the epitaxial growth process itself, rather than as a separate post-processing step. The fin base is prepared with isolation regions before S/D epitaxial growth, allowing the isolation structures to be created in-situ during the same manufacturing process that forms the S/D regions, thus minimizing additional process complexity.
Solution Approach 2:
The epitaxial growth process itself is utilized to form both the S/D regions and the isolation structures simultaneously. The isolation structures are created as part of the self-service mechanism of the epitaxial process, where the same chemical vapor deposition or molecular beam epitaxial process that grows the S/D regions also forms the isolation structures on the fin base, eliminating the need for separate fabrication steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively prevents current leakage and short channel effects by electrically isolating epitaxial S/D regions from the fin bases, enhancing the performance and reliability of GAA FETs while maintaining manufacturing cost efficiency.
Implementation Method 1
a silicon-rich dielectric layer disposed on the undoped semiconductor layer... electrically isolates the S/D regions from the fin bases
Data Source
AI summary
A semiconductor device and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, a fin base disposed on the substrate, nanostructured channel regions disposed on a first portion of the fin base, a gate structure surrounding the nanostructured channel regions, a source/drain (S/D) region disposed on a second portion of the fin base, and an isolation structure disposed between the S/D region and the second portion of the fin base. The isolation structure includes an undoped semiconductor layer disposed on the second portion of the fin base, a silicon-rich dielectric layer disposed on the undoped semiconductor layer, and an air spacer disposed on the silicon-rich dielectric layer.