Interrupted Upper Nanowire Layout to Cut Parasitic Capacitance
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Solution Overview
Problem
The increasing demand for high-performance, high-speed, and multifunctional semiconductor devices requires finer patterns and three-dimensional channel structures to overcome the limitations of planar metal oxide semiconductor FETs, necessitating improved electrical characteristics.
Innovation Solution
A semiconductor device with a substrate featuring active regions, gate electrode layers, channel layers, gate spacer layers, and source/drain regions is designed, where the uppermost channel layer is separated into portions below the gate spacer layers, reducing parasitic capacitance and enhancing AC performance and power characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the channel layer is made continuous and extends under the gate electrode, then the channel structure provides good electrical conduction, but parasitic capacitance increases and AC performance deteriorates
Solution Approach 1:
The channel layer is segmented into multiple portions (first channel layer portion, second channel layer portion, third channel layer portion) with different extensions relative to the gate electrode. The first portion extends beyond the gate electrode in the first direction, the second portion extends beyond the gate electrode in the second direction, and the third portion is positioned between these two portions. This segmentation allows different channel portions to serve different functions, reducing parasitic capacitance while maintaining electrical conduction.
Solution Approach 2:
The channel structure transitions from a conventional two-dimensional planar channel to a three-dimensional structure with multiple portions extending in different directions (first direction, second direction, and third direction). This dimensional expansion allows the channel to maintain conduction pathways while reducing overlap with the gate electrode, thereby reducing parasitic capacitance.
2Speed
If the channel structure length is reduced to improve speed, then AC performance improves, but electrical characteristics and reliability may deteriorate
Solution Approach 1:
Different portions of the channel layer are assigned different local qualities and functions. The first channel layer portion provides conduction in the first direction, the second channel layer portion provides conduction in the second direction, and the third channel layer portion connects these portions. This local differentiation allows the channel structure to maintain reliability while achieving shorter effective channel length for improved speed.
Solution Approach 2:
The multi-port ion channel structure nests multiple conduction pathways within a compact area. The first, second, and third channel layer portions are positioned relative to each other and to the gate electrode to create a nested arrangement that maximizes conduction efficiency while minimizing parasitic capacitance and maintaining reliability.
Data Source
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AI summary
A semiconductor device includes a substrate (101) including an active region (105) extending in a first direction, a gate electrode layer (165) crossing the active region (105) and extending in a second direction, and a plurality of nanowire or nanosheet layers of channel material (141-144) on the active region (105), spaced apart from each other in a vertical direction and disposed sequentially on the active region (105). The lower layers of channel material (141-143) are surrounded by the gate electrode layer (165) and form gate-all-around channels of the device, whereas te upper layer of channel material is interrupted and does not form a channel of the device. Gate spacer layers (164) are disposed on side surfaces of the gate electrode layer (165) in the first direction, and source/drain regions (150) are disposed on the active region (105), on sides of the gate electrode layer (165), and connected to the plurality layers of channel material (141-144). The uppermost layer of channel material thus includes portions (144P1, 144P2) separated from each other in the first direction and disposed below the gate spacer layers (164). More than one layer of semiconductor material may be interrupted.