GAA Transistor Isolation Spacers With Sealed Air Gaps
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Solution Overview
Problem
Gate-all-around (GAA) field effect transistors (FETs) face parasitic capacitance issues due to the formation of parasitic capacitors between the metal gate structure, spacer structure, and source/drain epitaxial structures, which can be detrimental to their operation, especially when the spacer material has a high dielectric constant.
Innovation Solution
The use of a low dielectric constant spacer material with a dielectric constant between 3.7 and 5.2, incorporating an air gap or air cavity, and a silicon nitride-based material with tunable nitrogen and oxygen atomic concentrations, deposited using thermal atomic layer deposition and treated with post-deposition processes to reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high dielectric constant spacer material is used, then electrical isolation between gate structure and source/drain structures is improved, but parasitic capacitance increases which is detrimental to transistor operation
Solution Approach 1:
The patent changes the dielectric constant parameter of the spacer material from high to low (between 3.7 and 5.2). This parameter change directly reduces parasitic capacitance while maintaining adequate electrical isolation through the combination of low-k material and air gaps/cavities in the spacer structure
Solution Approach 2:
The patent introduces air gaps or air cavities within the spacer structure, creating a porous or void-containing configuration. This reduces the effective dielectric constant of the spacer material and thereby reduces parasitic capacitance between the gate structure and source/drain structures
2Strength
If spacer material density is increased to improve mechanical strength, then structural integrity is improved, but dielectric constant increases which increases parasitic capacitance
Solution Approach 1:
The patent employs a porous spacer structure containing air gaps or air cavities that reduce the effective dielectric constant and parasitic capacitance. The structural integrity is maintained through the framework of the porous structure and the mechanical support provided by surrounding device structures
Solution Approach 2:
The spacer structure functions as a composite material system combining low-k dielectric material with air gaps/cavities. This composite configuration achieves both mechanical strength and low parasitic capacitance by distributing structural loads through the material framework while minimizing dielectric constant through the air voids
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of low dielectric constant spacer structures effectively mitigates parasitic capacitances, improving the performance of GAA FETs by reducing dielectric constant and enhancing electrical isolation.
Implementation Method 1
deposited using thermal atomic layer deposition
Data Source
AI summary
The present disclosure is directed to method for the fabrication of spacer structures between source/drain (S/D) epitaxial structures and metal gate structures in nanostructure transistors. The method includes forming a fin structure with alternating first and second nanostructure elements on a substrate. The method also includes etching edge portions of the first nanostructure elements in the fin structure to form cavities. Further, depositing a spacer material on the fin structure to fill the cavities and removing a portion of the spacer material in the cavities to form an opening in the spacer material. In addition, the method includes forming S/D epitaxial structures on the substrate to abut the fin structure and the spacer material so that sidewall portions of the S/D epitaxial structures seal the opening in the spacer material to form an air gap in the spacer material.