Germanium GAA Nanowire Channels With Thin Buffer Defect Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in fabricating gate-all-around integrated circuit structures with germanium nanowire channel structures is the high lattice mismatch between sacrificial layers and the germanium channel layer, leading to defect formation, and existing solutions involving thick buffer layers result in prolonged processing times and wafer bow issues.
Innovation Solution
A substrate modification layer and a thin relaxed silicon germanium buffer layer are used in conjunction with a silicon germanium sacrificial layer to achieve defect-free germanium nanowires or nanoribbons, with a defect modification layer aiding in relaxing the buffer layer and directing dislocations downward, allowing for improved electrical performance and mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If thick buffer layers are used to achieve defect-free germanium nanowires, then manufacturing precision is improved, but productivity deteriorates due to prolonged processing times
Solution Approach 1:
A substrate modification layer is formed prior to the buffer layer to pre-establish conditions that promote defect-free germanium nanowire growth. This preliminary action enables the use of thinner buffer layers while still achieving the desired defect-free outcome, thereby reducing overall processing time and improving productivity.
Solution Approach 2:
The substrate modification layer acts as an intermediary between the substrate and the buffer layer, facilitating defect management and enabling thinner buffer layers to achieve defect-free germanium nanowires. This intermediary structure reduces the thickness requirement of the buffer layer, thus reducing processing time while maintaining manufacturing precision.
2Manufacturing precision
If thick buffer layers are used to achieve defect-free germanium nanowires, then manufacturing precision is improved, but device complexity increases due to wafer bow issues
Solution Approach 1:
The substrate modification layer is formed in advance to pre-establish conditions that reduce lattice mismatch and promote defect-free germanium nanowire growth. This preliminary action enables the use of thinner buffer layers, which in turn reduces wafer bow issues and simplifies device fabrication processes, thereby reducing device complexity.
Solution Approach 2:
The substrate modification layer serves as an intermediary that mediates between the substrate and the buffer layer, reducing lattice mismatch and enabling thinner buffer layers. This reduces wafer bow issues and simplifies subsequent processing steps, thereby reducing device complexity while maintaining manufacturing precision.
3Ease of manufacture
If conventional tri-gate fabrication processes are used on bulk silicon substrates, then ease of manufacture is improved, but manufacturing precision deteriorates at dimensions below 10 nanometer node
Solution Approach 1:
The invention changes the structural parameters by transitioning from conventional planar or tri-gate structures to gate-all-around nanowire structures. This parameter change enables superior short channel control and mobility improvement at sub-10 nanometer nodes while maintaining ease of manufacture through adapted fabrication processes.
Solution Approach 2:
The invention moves to another dimension by implementing gate-all-around structures that surround the nanowire channel in three dimensions, providing superior electrostatic control compared to conventional planar or tri-gate structures. This dimensional change enables precise manufacturing control at sub-10 nanometer nodes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of defect-free germanium nanowire channels with enhanced mobility and inverted channel portions, improving transistor performance while reducing processing time and avoiding wafer bow issues.
Implementation Method 1
the high lattice mismatch between sacrificial layers and the germanium channel layer
Implementation Method 2
directing dislocations downward
Data Source
AI summary
Gate-all-around integrated circuit structures having germanium nanowire channel structures, and methods of fabricating gate-all-around integrated circuit structures having germanium nanowire channel structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin, each of the nanowires including germanium, and the fin including a defect modification layer on a first semiconductor layer, a second semiconductor layer on the defect modification layer, and a third semiconductor layer on the second semiconductor layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.