SOI Wafer Structure With Trap-Rich Layer Against Surface Conduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrated circuits on bulk semiconductor substrates face issues with parasitic surface conduction (PSC) leading to substrate loss and harmonic distortion due to current leakage, which are not adequately addressed by traditional silicon on insulator (SOI) devices.
Innovation Solution
A silicon on insulator (SOI) device is designed with a trap-rich layer containing nano-dots or a doped negative charge layer positioned next to an induced positive fixed charge layer, effectively trapping negative carriers to neutralize positive charges and interrupt PSC channels, thereby increasing substrate resistivity and reducing losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional bulk semiconductor substrates are used, then device fabrication is simpler, but parasitic surface conduction causes substrate loss and harmonic distortion
Solution Approach 1:
The substrate is segmented into multiple functional layers: bulk substrate, buried oxide layer, and trap-rich layer. This segmentation isolates the active semiconductor layer from the bulk substrate, preventing parasitic surface conduction while maintaining fabrication feasibility through established SOI manufacturing processes
Solution Approach 2:
A trap-rich layer is introduced as an intermediary between the buried oxide layer and the active semiconductor layer. This intermediate layer contains trapping centers that capture carriers and eliminate parasitic surface conduction channels, resolving the harmful effects without complicating the overall device structure
2Reliability
If SOI substrate with buried oxide layer is used, then current leakage is reduced, but induced positive fixed charge layer causes parasitic surface conduction
Solution Approach 1:
The induced positive fixed charge layer, which normally causes parasitic surface conduction, is converted into a beneficial element. By positioning a trap-rich layer adjacent to it, the positive charges attract and trap negative carriers, which then neutralize the positive charges and eliminate the harmful PSC channels
Solution Approach 2:
The trap-rich layer acts as an intermediary that mediates between the induced positive charge layer and the active semiconductor. It provides trapping centers that capture carriers and prevent them from participating in parasitic conduction, while also neutralizing the positive charges through trapped negative carriers
3Object-generated harmful factors
If trap-rich layer with nano-dots is added, then parasitic surface conduction is interrupted, but device structure becomes more complex
Solution Approach 1:
The trap-rich layer is implemented by modifying the electrical parameters of an existing layer through ion implantation or in-situ doping, rather than adding a completely new physical layer. This changes the carrier trapping characteristics of the layer while maintaining compatibility with standard SOI device fabrication processes
Solution Approach 2:
The trap-rich layer is formed using composite material structures, such as silicon germanium (SiGe) layers or doped silicon regions, that combine the electrical trapping properties with mechanical compatibility to the existing SOI structure. This approach integrates the anti-PSC functionality without significantly increasing device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively cancels parasitic surface conduction channels, enhances substrate resistivity, and minimizes harmonic distortion and substrate loss by neutralizing positive charges with trapped negative carriers, improving power-speed performance in high-frequency devices.
Implementation Method 1
a trap-rich layer having nano-dots and an oxide layer are stacked on a high resistivity substrate sequentially... trap negative carriers and wipe out induced positive charges
Implementation Method 2
a doped negative charge layer including negative carriers therein is applied instead, to wipe out the positive charges
Data Source
AI summary
A silicon on insulator (SOI) device includes a wafer and a trap-rich layer. The wafer includes a top silicon layer disposed on a buried oxide layer. The trap-rich layer having nano-dots and an oxide layer are stacked on a high resistivity substrate sequentially, wherein the oxide layer is bonded with the buried oxide layer. Or, a silicon on insulator (SOI) device includes a wafer and a high resistivity substrate. The wafer includes a top silicon layer disposed on a buried oxide layer. The high resistivity substrate is bonded with the buried oxide layer, wherein a positive fixed charge layer is induced at a surface of the buried oxide layer contacting the high resistivity substrate, and a doped negative charge layer is right next to the positive fixed charge layer. The present invention also provides a method of forming said silicon on insulator (SOI) device.