Double-Side Transistor Contacts for Dense 3DIC Interconnects
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Solution Overview
Problem
Conventional contact configurations in 3DIC devices, such as FinFET and Gate-All-Around (GAA) devices, limit the ability for high-density connections in stacked configurations, hindering the advancement of three-dimensional integrated circuit technology.
Innovation Solution
The implementation of transistors with double-side contacts, where a drain and source are enclosed in silicide layers with integral via portions directly coupled to contacts, allowing for improved connectivity and reduced IC thickness, enabling more flexible and dense interconnections without the limitations of conventional microscopic thru-silicon-vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional contact configurations are used in 3DIC devices, then manufacturing process is simpler, but connectivity density and stacking flexibility are limited
Solution Approach 1:
The contact configuration is segmented into multiple independent contacts (first contact, second contact, third contact, fourth contact) positioned at different locations on the substrate. This segmentation allows each contact to be independently connected to different circuit elements, enabling higher connectivity density without requiring complex through-silicon-via structures.
Solution Approach 2:
The invention transitions from conventional vertical through-silicon-via connections to a planar arrangement where multiple contacts are positioned at different locations on the substrate surface. This dimensional change from vertical stacking to lateral distribution enables improved connectivity density while simplifying the manufacturing process.
2Area of stationary object
If conventional thru-silicon-vias are used for 3D stacking, then vertical connections are achieved, but additional area outside active device is required
Solution Approach 1:
Multiple contact functions are merged into a single planar contact structure arrangement. The first, second, third, and fourth contacts are positioned at different locations on the substrate and can be connected to various circuit elements, eliminating the need for separate through-silicon-via structures and reducing the area required for vertical connections.
Solution Approach 2:
The invention moves from vertical through-silicon-via connections requiring area outside the active device to a planar contact arrangement where all connections are made within the substrate area. This dimensional transition enables improved stacking flexibility without sacrificing device area.
3Reliability
If conventional contact configurations are used, then manufacturing process is standard, but local device performance is limited
Solution Approach 1:
Different contacts are positioned at specific locations on the substrate to optimize local device performance. The first contact is positioned to connect to the first circuit element, the second contact to the second circuit element, and so on, allowing each contact to be optimized for its specific function and location without requiring complex fabrication processes.
Data Source
AI summary
Disclosed are apparatuses including transistor and methods for fabricating the same. The transistor may include a drain substantially enclosed in a drain silicide layer, wherein an integral drain via portion of the drain silicide layer is coupled to a second drain contact and wherein a first drain via couples the drain silicide layer to a first drain contact. The transistor may include a source substantially enclosed in a source silicide layer, wherein an integral source via portion of the source silicide layer is coupled to a second source contact and wherein a first source via couples the source silicide layer to a first source contact. The transistor may include a gate disposed between the source and the drain.