Semiconductor Channel Cladding for Uniform Sub-1 Nm Ge Growth
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down device structures such as 3D nanosheets, nanowires, and finFETs due to difficulties in forming a thin, uniform germanium (Ge) cladding layer, which is crucial for advanced device performance, as existing methods like ion implantation and chemical vapor deposition are not feasible in these scaled-down geometries.
Innovation Solution
The use of reduced pressure chemical vapor deposition (CVD) tools at specific design process conditions, including a Ge treatment at 450°C with germane as a reacting gas, followed by an annealing process, allows for the epitaxial growth of a thin, uniform Ge or GeSi cladding layer on silicon channel layers, avoiding uncontrolled island formation and ensuring adequate thickness and composition for improved device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ion implantation or chemical vapor deposition is used to form Ge cladding layer, then device performance can be improved, but the method is not feasible in scaled-down geometries such as 3D nanosheets, nanowires, and finFETs
Solution Approach 1:
The patent changes the fundamental parameters of the deposition process by using reduced pressure CVD instead of conventional atmospheric pressure CVD or ion implantation. This parameter change enables the formation of thin Ge cladding layers in scaled-down geometries by improving gas distribution and surface coverage in three-dimensional structures, thereby maintaining manufacturing feasibility while achieving the desired device performance enhancement
Solution Approach 2:
The patent replaces the mechanical ion implantation process with a chemical vapor deposition process. This substitution eliminates the need for complex ion source equipment and masking steps, allowing for more straightforward formation of Ge cladding layers in nanoscale and three-dimensional structures, thus improving ease of manufacture while maintaining the ability to enhance device performance
2Length of stationary object
If Ge cladding layer thickness is reduced to less than 1 nm, then adequate space for gate structures is ensured, but uncontrolled island formation may occur
Solution Approach 1:
The patent employs reduced pressure conditions and specific temperature control during CVD to change the kinetic parameters of Ge deposition. This enables precise control over nucleation and growth rates, allowing thin cladding layers of less than 1 nm to be formed uniformly without uncontrolled island formation, thus simultaneously achieving the desired thickness reduction and compositional stability
Solution Approach 2:
The patent implements process monitoring and control mechanisms that provide feedback during the CVD process. By monitoring deposition rate and surface morphology in real-time, the process can be adjusted to prevent island formation while maintaining the target thickness of less than 1 nm, ensuring both dimensional control and compositional uniformity
3Manufacturing precision
If reduced pressure CVD is used with specific process conditions, then thin uniform Ge cladding layer can be formed, but process complexity increases
Solution Approach 1:
The patent demonstrates that reduced pressure CVD can serve multiple functions: it provides uniform gas distribution across large substrate areas, ensures complete surface coverage in three-dimensional structures, and enables precise thickness control. This multi-functionality achieves high manufacturing precision for thin uniform cladding layers while avoiding the need for multiple separate process steps, thereby not increasing overall process complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the formation of a thin Ge or GeSi cladding layer with a thickness less than 1 nm, maintaining device performance by preventing island mergers and ensuring sufficient space for gate structures, thus addressing the limitations of existing techniques in scaled-down device structures.
Implementation Method 1
The use of reduced pressure chemical vapor deposition (CVD) tools at specific design process conditions, including a Ge treatment at 450°C with germane as a reacting gas
Implementation Method 2
allows for the epitaxial growth of a thin, uniform Ge or GeSi cladding layer on silicon channel layers
Implementation Method 3
followed by an annealing process, allows for the epitaxial growth of a thin, uniform Ge or GeSi cladding layer
Data Source
AI summary
The present disclosure provides channel structures of a semiconductor device and fabricating methods thereof. The method can include forming a superlattice structure with first nanostructured layers and second nanostructured layers on a fin structure. The method can also include removing the second nanostructured layers to form multiple gate openings; forming a germanium epitaxial growth layer on the first nanostructured layers at a first temperature and a first pressure; and increasing the first temperature to a second temperature and increasing the first pressure to a second pressure over a first predetermined period of time. The method can further include annealing the germanium epitaxial growth layer at the second temperature and the second pressure in the chamber over a second predetermined period of time to form a cladding layer surrounding the first nanostructured layers.