Hybrid-Fin GAA Transistor Layout for Easier Metal Gate Filling
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, challenges arise in integrating more components into a given area while maintaining production yield and reducing electrical resistance, particularly in forming gate electrodes around nanowires due to increasing aspect ratios and spacing between semiconductor strips.
Innovation Solution
The method involves forming semiconductor fins with alternating epitaxial layers, creating hybrid fins with dielectric structures, and selectively removing semiconductor materials to form nanowires surrounded by dielectric fins, allowing for easier metal gate filling and reducing electrical resistance by increasing the distance between nanowires and dielectric fins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature size is reduced to increase integration density, then more components can be integrated into a given area, but manufacturing difficulty and electrical resistance increase
Solution Approach 1:
The gate electrode formation process is segmented into multiple steps: first forming a mandrel structure, then selectively removing semiconductor material to create spaces, and finally filling those spaces with metal. This segmentation allows for better control at each stage, particularly in managing the high aspect ratios and spacing issues that arise when feature sizes are reduced for higher integration density.
Solution Approach 2:
The patent employs preliminary actions by first forming the mandrel structure and selectively removing semiconductor material before attempting to form the metal gate. This preliminary preparation creates optimized spaces that facilitate subsequent metal filling, addressing the manufacturing difficulties associated with reduced feature sizes and improved integration density.
2Quantity of substance
If feature size is reduced to increase integration density, then more components can be integrated into a given area, but electrical resistance increases
Solution Approach 1:
The patent transitions from planar gate structures to three-dimensional gate-all-around structures that completely surround the nanowire channels. This dimensional change increases the effective gate control and conductivity without increasing the planar footprint, thereby reducing electrical resistance while maintaining high integration density.
Solution Approach 2:
The gate structure employs composite materials including metal gates surrounded by dielectric fins and nanowire channels. This composite structure optimizes electrical conductivity while managing the increased resistance challenges associated with reduced feature sizes and higher integration density.
3Reliability
If metal gate filling is attempted in high aspect ratio structures, then gate-all-around control is achieved, but filling difficulty and manufacturing complexity increase
Solution Approach 1:
The gate formation is segmented into distinct phases: mandrel formation, selective semiconductor removal to create spaces, and metal filling of those spaces. This segmentation transforms the difficult task of filling high aspect ratio structures into a series of manageable steps, each optimized for its specific function, thereby achieving gate-all-around control while reducing filling difficulty.
Solution Approach 2:
The mandrel structure serves as an intermediary element that facilitates the eventual metal gate formation. By first creating the mandrel and then selectively removing surrounding semiconductor material, the process creates optimized spaces that serve as intermediaries for the metal filling step, making the overall process more manufacturable despite the high aspect ratios involved.
4Ease of manufacture
If spacing between semiconductor strips is increased to facilitate metal filling, then manufacturing becomes easier, but integration density decreases
Solution Approach 1:
The patent achieves gate-all-around control in a three-dimensional configuration that completely surrounds the nanowire channels. This vertical and radial gate enclosure provides comprehensive control without requiring increased horizontal spacing between strips, thereby maintaining high integration density while facilitating metal filling through the created spaces.
Solution Approach 2:
By segmenting the gate formation into mandrel creation followed by selective semiconductor removal, the patent creates spaces that are optimally sized and positioned for metal filling. This segmentation allows metal filling to proceed more easily without requiring increased spacing between semiconductor strips, thus preserving integration density while improving manufacturability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances production yield by facilitating easier metal gate filling and reduces electrical resistance, while also increasing integration density and improving time-dependent dielectric breakdown performance.
Implementation Method 1
a metal gate around the nanowires and around center portions of the first dielectric fin
Implementation Method 2
a first dielectric fin on the first isolation region... end portions of the first dielectric fin are wider than the center portions of the first dielectric fin
Data Source
AI summary
A method of forming a semiconductor device includes forming semiconductor strips protruding above a substrate and isolation regions between the semiconductor strips; forming hybrid fins on the isolation regions, the hybrid fins comprising dielectric fins and dielectric structures over the dielectric fins; forming a dummy gate structure over the semiconductor strip; forming source/drain regions over the semiconductor strips and on opposing sides of the dummy gate structure; forming nanowires under the dummy gate structure, where the nanowires are over and aligned with respective semiconductor strips, and the source/drain regions are at opposing ends of the nanowires, where the hybrid fins extend further from the substrate than the nanowires; after forming the nanowires, reducing widths of center portions of the hybrid fins while keeping widths of end portions of the hybrid fins unchanged, and forming an electrically conductive material around the nanowires.