Transistor Isolation Below Source and Drain to Block Subfin Leakage
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Solution Overview
Problem
Parasitic leakage between the source and drain regions in non-planar transistor structures, particularly in III-V transistors, is challenging to control due to the rapid diffusion of dopants and the complexity of integrating spacers in the gate structure, which affects the performance and scalability of FinFET devices.
Innovation Solution
The introduction of an isolation region of insulator material below the source and drain regions in tri-gate and gate-all-around transistor structures, which extends along the bottom surface of the channel region to block parasitic leakage, using techniques such as etching to form recesses and depositing insulator material to replace the lower fin portion, and epitaxially regrowing the source and drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dopants are used to control charge carrier flow in III-V transistors, then electrical conductivity is improved, but parasitic leakage increases due to rapid dopant diffusion
Solution Approach 1:
An insulator region is introduced as an intermediary barrier between the source/drain regions and the subfin region. This insulator prevents direct electrical interaction that would cause parasitic leakage, while allowing the dopants to still provide necessary conductivity control in the channel region above the insulator.
Solution Approach 2:
The transistor structure is segmented into distinct regions: the channel region above the fin, the source and drain regions, and the subfin region below. The insulator region creates an additional segmentation that isolates the source/drain from the subfin, preventing parasitic leakage paths while maintaining functional separation of the transistor components.
2Object-generated harmful factors
If spacers are integrated into the gate structure to reduce leakage, then parasitic leakage is reduced, but device complexity increases
Solution Approach 1:
The leakage prevention function is extracted from the gate structure spacers and placed in a separate insulator region below the source/drain. This removes the complexity of integrating spacers into the gate while achieving the same leakage reduction goal through a simpler, dedicated isolation structure.
3Reliability
If the fin structure is used to increase channel area, then transistor performance is improved, but parasitic leakage paths are created below the source and drain
Solution Approach 1:
The insulator region acts as a mediator that allows the fin structure to provide increased channel area for improved transistor performance, while simultaneously blocking the parasitic leakage paths that would otherwise exist in the subfin region below the source and drain contacts.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces or eliminates parasitic subfin leakage, improving the performance of transistors by isolating the source and drain regions from the subfin region, thereby enhancing the control over charge carrier flow and reducing leakage currents.
Implementation Method 1
an isolation region of insulator material below the source and drain regions... extends along the bottom surface of the channel region to block parasitic leakage
Implementation Method 2
epitaxially regrowing the source and drain regions
Data Source
AI summary
A transistor includes a body of semiconductor material, where the body has laterally opposed body sidewalls and a top surface. A gate structure contacts the top surface of the body. A source region contacts a first one of the laterally opposed body sidewalls and a drain region contacts a second one of the laterally opposed body sidewalls. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. Depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., FinFET transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).