Superlattice 28Si Epitaxial Layers With Diffusion Barrier Cap
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Solution Overview
Problem
Current semiconductor devices seek further enhancements in performance through advanced materials and processing techniques to improve charge carrier mobility and reduce defects, while maintaining cost-effectiveness and preventing silicon intermixing.
Innovation Solution
The semiconductor device incorporates a superlattice structure with stacked silicon monolayers and non-semiconductor monolayers, such as oxygen, to reduce effective mass and enhance mobility, and includes a cap layer to prevent dopant and material diffusion, acting as a barrier and interface for high-K dielectrics, thereby improving device performance and reducing scattering effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If strained material layers of silicon and silicon-germanium are used to enhance carrier mobility, then device speed and performance are improved, but manufacturing complexity and processing difficulty increase
Solution Approach 1:
The patent segments the silicon layer into multiple thin sub-layers separated by interfacial layers (such as SiO2/Si superlattice structures). Each sub-layer is thinner than the critical thickness required to maintain coherent strain, allowing strain to be distributed across multiple interfaces rather than requiring a single complex strained layer structure. This segmentation enables mobility enhancement while simplifying the overall processing by using standard thin film deposition techniques.
Solution Approach 2:
The patent introduces interfacial layers (mediators) between silicon sub-layers, such as thin SiO2 layers or other dielectric materials. These intermediary layers serve multiple functions: they maintain the strain field across silicon sub-layers, prevent direct silicon-silicon contact that would require precise thickness control, and provide a buffer that simplifies the deposition process. The intermediaries enable strain engineering without requiring complex single-layer strain control.
2Reliability
If silicon layers are grown to achieve high purity 28Si, then device performance is enhanced, but fabrication cost increases
Solution Approach 1:
The patent applies preliminary isotopic enrichment to the silicon substrate or seed layer before epitaxial growth. By starting with 28Si-enriched material at the base layer, the subsequent epitaxial growth naturally inherits this high purity without requiring expensive post-growth purification processes. This preliminary action locks in the desired isotopic composition early in the fabrication sequence, avoiding costly later-stage interventions.
Solution Approach 2:
The patent uses an enriched 28Si substrate or seed layer as a template that copies its isotopic composition to the overgrown epitaxial silicon layers. The epitaxial growth process replicates the crystal structure and isotopic makeup of the underlying layer, allowing high-purity 28Si to be propagated through multiple layers without requiring each layer to be independently purified. This copying mechanism reduces fabrication costs by eliminating redundant purification steps.
3Reliability
If dopant diffusion is allowed during fabrication, then device activation is achieved, but material mixing and defect formation occur
Solution Approach 1:
The patent extracts or removes the dopant diffusion problem by introducing barrier layers (such as SiO2 or other dielectric materials) between regions where dopant diffusion would cause contamination. These extracted barrier layers physically separate dopant sources from sensitive regions, preventing unwanted diffusion while allowing controlled dopant introduction in designated areas. The harmful diffusion process is taken out of the system by blocking it with selective barriers.
Solution Approach 2:
The patent introduces intermediary barrier layers between silicon regions with different dopant requirements. These intermediary layers act as diffusion barriers that prevent dopant mixing between adjacent regions while still allowing electrical isolation to be maintained. The mediators enable precise dopant placement by blocking unwanted diffusion paths, thereby maintaining material separation precision while still achieving necessary device activation in designated regions.
4Speed
If superlattice structures with multiple layers are implemented, then charge carrier mobility is enhanced, but fabrication complexity increases
Solution Approach 1:
The patent optimizes the parameters of the superlattice structure, specifically controlling the thickness of silicon sub-layers to be below the critical thickness for strain maintenance (typically a few nanometers) and spacing them with thin interfacial layers. By changing these dimensional parameters to specific ranges, the structure achieves strain-induced mobility enhancement while keeping the overall complexity manageable. The parameter optimization ensures that each layer is thin enough to maintain strain coherence but not so thin as to create excessive processing difficulty.
Solution Approach 2:
The patent creates a composite structure combining silicon sub-layers with interfacial dielectric layers (such as SiO2/Si superlattice). This composite material approach allows the silicon layers to maintain strain for mobility enhancement while the dielectric intermediaries provide structural stability and simplify processing. The composite structure achieves the benefits of complex superlattice design (enhanced mobility through strain) while using well-established dielectric materials that are compatible with standard semiconductor fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The superlattice structure achieves higher charge carrier mobility, reduces silicon intermixing, and allows for the growth of purified 28Si layers at lower fabrication costs, enhancing the performance of semiconductor devices like MOSFETs and quantum bits while maintaining low defect density.
Implementation Method 1
The superlattice includes stacked groups of layers, with each group of layers including stacked base silicon monolayers defining a base silicon portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions
Implementation Method 2
The semiconductor device includes a cap layer to prevent dopant and material diffusion, acting as a barrier and interface for high-K dielectrics
Implementation Method 3
U.S. Pat. No. 5,357,119 to Wang et al. discloses a Si—Ge short period superlattice with higher mobility achieved by reducing alloy scattering in the superlattice
Data Source
AI summary
A semiconductor device may include a first single crystal silicon layer having a first percentage of silicon 28; a second single crystal silicon layer having a second percentage of silicon 28 higher than the first percentage of silicon 28; and a superlattice between the first and second single crystal silicon layers. The superlattice may include stacked groups of layers, with each group of layers including stacked base silicon monolayers defining a base silicon portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions.