Standard Cell Wiring Layout With Stacked Power Rails
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Solution Overview
Problem
As semiconductor manufacturing processes are miniaturized, the integration degree and performance of integrated circuits are limited by the complexity and reliability of standard cell layouts, particularly in routing transistors with multiple wiring layers.
Innovation Solution
The integration circuit design includes a plurality of wiring layers stacked sequentially to electrically connect source and drain contacts of transistors across standard cells, enhancing connectivity and reducing resistance through parallel and perpendicular wiring configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If standard cell size is reduced through miniaturization, then integration density increases, but wiring complexity and resistance increase
Solution Approach 1:
The patent transitions from planar wiring to three-dimensional stacked wiring layers. Multiple wiring layers are stacked vertically to provide parallel conduction paths, effectively adding a vertical dimension to the wiring architecture. This resolves the contradiction by maintaining compact standard cell footprints while reducing wiring complexity through spatial distribution across multiple layers.
Solution Approach 2:
The wiring system is segmented into multiple independent wiring layers, each handling specific signal or power routing functions. This segmentation allows complex routing tasks to be divided across layers, reducing the complexity burden on any single layer while maintaining overall system functionality.
2Area of moving object
If standard cell size is reduced through miniaturization, then integration density increases, but electrical resistance increases
Solution Approach 1:
By stacking multiple wiring layers vertically, the patent creates parallel conduction paths that reduce electrical resistance. The vertical stacking allows current to be distributed across multiple layers, effectively lowering the overall resistance despite reduced standard cell dimensions.
Solution Approach 2:
Multiple wiring layers are merged to form a unified three-dimensional wiring system. The layers work together to provide redundant and parallel conduction paths, combining their conductive capabilities to overcome the resistance increase associated with miniaturization.
3Productivity
If multiple wiring layers are stacked to improve connectivity, then integration degree increases, but manufacturing complexity increases
Solution Approach 1:
The patent implements multiple wiring layers stacked in the vertical dimension, achieving high integration degree without expanding the lateral footprint. This vertical stacking approach allows advanced connectivity while managing manufacturing complexity through systematic layer formation processes.
Solution Approach 2:
The stacked wiring layer structure serves multiple functions simultaneously: signal routing, power distribution, and interconnect formation. This multi-functionality increases integration degree while avoiding the need for separate manufacturing processes for each function, thereby managing manufacturing complexity.
4Reliability
If wiring layers are increased to reduce resistance, then electrical conductivity improves, but device complexity increases
Solution Approach 1:
The patent uses vertical stacking of wiring layers to improve electrical conductivity by creating parallel conduction paths. This three-dimensional approach enhances conductivity while managing device complexity through organized spatial distribution of wiring functions across layers.
Solution Approach 2:
The wiring system is segmented into multiple specialized layers, each optimized for specific electrical functions. This segmentation improves overall conductivity by distributing current across multiple paths while managing complexity through functional specialization of each layer.
Data Source
AI summary
An integrated circuit includes a first standard cell including a first first-type transistor, a first second-type transistor, a third second-type transistor, and a third first-type transistor, a second standard cell including a second first-type transistor, a second second-type transistor, a fourth second-type transistor and a fourth first-type transistor, a plurality of wiring layers which are disposed on the first and second standard cells and includes a first wiring layer, a second wiring layer, and a third wiring layer sequentially stacked. A source contact of the first first-type transistor and a source contact of the second first-type transistor are electrically connected through a first power rail of the plurality of wiring layers, and a source contact of the third first-type transistor and a source contact of the fourth first-type transistor are electrically connected through a second power rail of the plurality of wiring layers.