Nano-FET Gate Structures With Sacrificial Layer Work Function Isolation
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, challenges arise in integrating more components into a given area, including issues with work function tuning layers that can degrade p-type devices if formed between nanostructures, leading to performance degradation.
Innovation Solution
The method involves forming work function tuning layers for n-type devices before p-type devices, using a sacrificial layer deposited by flowable chemical vapor deposition to prevent the tuning layers from forming between p-type devices, ensuring improved deposition profiles and gap filling without seams or gaps, and controlling threshold voltages by forming and patterning this sacrificial layer to isolate the p-type devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If work function tuning layers are formed for both n-type and p-type devices using the same process, then both device types can be fabricated, but the tuning layers degrade p-type devices and cause performance degradation
Solution Approach 1:
The patent segments the work function tuning process by dividing it into separate sequential steps for n-type and p-type devices. The first work function tuning layer is formed only for n-type devices, then a sacrificial layer is deposited and patterned to protect p-type device regions. A second work function tuning layer is then formed only for p-type devices. This segmentation prevents harmful cross-contamination while maintaining adaptability to fabricate both device types.
Solution Approach 2:
The patent applies preliminary action by first forming the work function tuning layer for n-type devices before any p-type device processing. The sacrificial layer is deposited and patterned in advance to define protected regions before the second work function tuning layer is formed. This preliminary structuring ensures that subsequent processing steps affect only the intended device types, preventing degradation while maintaining fabrication versatility.
2Productivity
If feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but additional manufacturing challenges and performance degradation issues arise
Solution Approach 1:
The patent segments the fabrication process into distinct sequential steps with sacrificial layers that define precise regions for different device types. This segmentation enables accurate control of work function tuning layer deposition at reduced feature sizes, allowing high integration density while maintaining manufacturing precision through protected region isolation.
Solution Approach 2:
The sacrificial layer acts as an intermediary element that enables precise region definition and material deposition control at reduced feature sizes. This intermediary structure allows the manufacturing process to achieve high integration density while maintaining precision by mediating between the deposition process and the final device structure, preventing cross-contamination between adjacent features.
3Ease of manufacture
If work function tuning layers are deposited without sacrificial layer protection, then the deposition process is simpler and faster, but the tuning layers form between p-type devices and cause degradation
Solution Approach 1:
The sacrificial layer serves as an intermediary protective structure that enables selective deposition of work function tuning materials. While it adds process steps, it maintains ease of manufacture by using standard deposition and patterning techniques, and dramatically improves reliability by preventing harmful material deposition between p-type devices through physical barrier formation.
4Ease of manufacture
If gap filling is performed without flowable CVD, then the deposition process is simpler, but seams or gaps form in the deposited layers reducing quality
Solution Approach 1:
The patent replaces conventional mechanical or standard CVD deposition methods with flowable CVD technology. This substitution maintains ease of manufacture by using vapor-phase deposition but dramatically improves manufacturing precision by enabling seamless gap filling through the flowable nature of the deposited material, eliminating defects without adding significant process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the control over threshold voltages and prevents degradation of p-type devices, improving the overall performance and integration density of nano-FETs by ensuring accurate and seamless gap filling and deposition.
Implementation Method 1
a sacrificial layer deposited by flowable chemical vapor deposition to prevent the tuning layers from forming between p-type devices
Data Source
AI summary
A method includes removing a first dummy gate structure to form a recess around a first nanostructure and a second nanostructure; depositing a sacrificial layer in the recess with a flowable chemical vapor deposition (CVD); and patterning the sacrificial layer to leave a portion of the sacrificial layer between the first nanostructure and the second nanostructure. The method further include depositing a first work function metal in first recess; removing the first work function metal and the portion of the sacrificial layer from the recess; depositing a second work function metal in the recess, wherein the second work function metal is of an opposite type than the first work function metal; and depositing a fill metal over the second work function metal in the recess.