Cache Coherence Devices for Cross-Host Memory Sharing in Cluster Systems
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Solution Overview
Problem
In cluster systems, memory resources across nodes cannot be shared, leading to inefficiency and waste due to each node being autonomous, limiting the utilization of available memory resources.
Innovation Solution
A computer system architecture that enables memory sharing between hosts using cache coherence devices and a switch, where a first host requests memory allocation from a second host, and the second host provides a translated physical address for the allocated memory space, allowing efficient access by the first host.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If each node in a cluster is an autonomous individual with dedicated memory resources, then each host can independently access its memory without interference, but memory resources cannot be shared across hosts, resulting in serious waste of memory resources
Solution Approach 1:
The patent merges memory resources from multiple hosts into a shared memory pool accessible by all hosts. The memory sharing mechanism allows any host to allocate and access memory from any other host, transforming isolated memory resources into a unified shared resource pool that improves overall utilization efficiency while maintaining reliable access through standardized protocols.
Solution Approach 2:
The patent implements universal memory access where memory resources can serve multiple purposes and multiple hosts simultaneously. The same memory physical pool can be dynamically allocated to different hosts based on demand, and the memory system can function both as local memory for each host and as shared remote memory, achieving multi-functionality and eliminating resource waste.
2Loss of energy
If memory resources are shared across hosts through cache coherence devices and switches, then memory resource utilization improves and dynamic allocation is enabled, but the system complexity increases due to address translation and coordination mechanisms
Solution Approach 1:
The patent introduces cache coherence devices as intermediaries between hosts and memory resources. These devices manage address translation, memory allocation requests, and coherence protocols, shielding the complexity from the main system while enabling efficient memory sharing. The switch fabric acts as another intermediary to route memory requests between hosts and target memory pools.
Solution Approach 2:
The patent implements self-service mechanisms where each host's cache coherence device autonomously manages its own memory allocation requests and address translation. The system uses self-organizing protocols for memory registration, allocation, and deallocation without requiring centralized control, reducing overall system complexity while maintaining efficient resource sharing.
Data Source
AI summary
The present disclosure relates to a computer system, a method for a computer system, and a computer-readable storage medium for executing the method for a computer system. The method for a computer system includes: using a first central processing unit (CPU) in a first host of the plurality of hosts to send memory request information according to a storage space required for executing a task; using a first cache coherence device in the first host and the switch to forward the memory request information to a second host of the plurality of hosts, so as to request the second host to allocate partial space in a memory to the first CPU for use, wherein the second host includes a second cache coherence device; in response to allocating the partial space in the memory of the second host, using the second cache coherence device and the switch to provide a physical address of the partial space to the first cache coherence device for translation to generate a translated physical address; and accessing the partial space by the first CPU using the translated physical address.