Memory Architecture Accessing/Allocation TRIZ Cases
- Memory Controller Wear-Leveling via Page Grouping and Interleaving
A memory controller groups pages across multiple banks to distribute write operations evenly.
- Virtual Hardware Security Module Emulation in Processor Cache
Software emulation of a hardware security module in processor cache resolves the trade-off between dedicated physical security and multi-VM availability.
- Persistent Memory Write Acceleration via Uncommitted Block Overwrite
Persistent memory accelerates CPU writes by overwriting uncommitted blocks directly in non-volatile storage.
- Cache Control Module Selective Write-Back for SSD Performance
A cache control module filters modified data blocks using integrity metadata before writing to persistent storage.
- Flash Memory Controller Double Write Buffer for QLC Data Integrity
Dual buffers in the flash controller stage data for QLC writes, preventing incomplete page damage from power loss and preserving storage capacity.
- Flash Memory Mapping Table Search Using Hardware Engines
Hardware search engines scan segmented mapping tables in SRAM and DRAM to reduce lookup latency as flash capacity grows.
- Dynamic Translation Lookaside Buffer Page Size Configuration
A translation lookaside buffer reconfigures address bit mapping to support variable memory page sizes.
- Dynamic Context Module for Isolated Container Switching
A context module generates dynamic user profiles to identify and switch between local or cloud containers on a host device.
- Heterogeneous Cache Demotion Using Access Counts
A cache system demotes data between DRAM and SCM based on read and write access counts.
- I/O Data Routing Logic for Cache Allocation Optimization
Routing logic predicts data usage via receive queue feedback to optimize cache allocation, reducing unnecessary memory transfers and mitigating cache pollution.
- Intelligent Container Garbage Collector for Storage Optimization
An intelligent garbage collector uses machine learning to classify containers and reduce storage space consumption.
- Cache Coherence Devices for Cross-Host Memory Sharing in Cluster Systems
Cache coherence devices forward memory requests between hosts to allocate partial memory spaces, eliminating resource waste from autonomous node isolation.
- Endurance Translation Layer for Flash Wear Reduction
An Endurance Translation Layer stores temporary data in DRAM to reduce flash memory writes.
- Flash Memory Controller Temperature Data Management
Controller manages temperature information via super pages for user blocks and individual pages for reserved blocks, reducing working memory usage.
- Layer-aware data movement control for container images
Assigning prefetching and cache-swapping priority weights to distinct container image layers resolves inefficiencies in dense cloud infrastructure deployments.
- Application-Aware NVM Storage Segmentation for Write Optimization
Classifies data objects by application metadata into dedicated storage sets, reducing garbage collection writes and improving device endurance.
- Dynamic Protection Information Transition in Storage Arrays
Storage array systems transition protection information states online using immediate availability format processes.
- I/O Load Value Prediction for Virtual Environments
Predicts I/O register values via address comparison to eliminate extra instructions and reduce data access latency in virtualized systems.
- Dynamic Cache Placement in Dataflow Execution
A dynamic cache placement system adjusts memory usage during dataflow execution.
- Multi-Layered Cache Metadata Structure for Clustered Storage
A multi-layered cache metadata structure organizes address arrays across hierarchical layers to locate cached data within a clustered storage system.
- Memory Module Embedded Access Metadata for Fine-Grained Tracking
Embedding access metadata in memory modules tracks row-level read and write patterns, reducing processor overhead from coarse page table management.
- SSD Stream Mapper Namespace Logical Hardware Allocation
A stream mapper assigns logical streams to hardware streams based on namespace characteristics.
- Multicast Tree Data Distribution in Distributed Shared Cache
A multicast tree-based data distribution system manages cache coherence by broadcasting updates to relevant processing cores.
- Vehicle Display Unit GUI Control via Partial Virtual Terminal Protocol
Display unit defines the graphical user interface via a user interface applet to reduce network traffic on the vehicle data bus.
- Storage Access Pattern Analysis for Data Preloading
Analyzes storage access numbers and variations to identify correlated ranges for intelligent data preloading.
- Transient Cache Line Prefetching to Reduce Memory Bandwidth Overshoot
A prefetch unit marks cache lines as transient and limits stream length to conserve memory bandwidth.
- Scratchpad Journaling for Storage Write Latency and Bandwidth
A scratchpad journaling mechanism aggregates write requests in non-volatile memory before committing them to persistent storage devices.
- Journal-Based Storage Recovery from Cache Failure
A journal-based data protection system restores lost write I/Os using split replica streams.
- Hypervisor-Controlled Firmware for Encrypted VM Memory
Hypervisor-controlled firmware manages encrypted guest memory using ephemeral keys and reserved ranges.
- Neural Network Protection Logic for Adversarial Attack Mitigation
A deep neural network system uses protection logic to detect and correct parameter tampering during operation.
- Probabilistic Cache Tag Lookup Using Home Directory Entry
An extra tag acts as a home directory entry in the cache controller, eliminating redundant lookups and reducing bandwidth overhead by over 80%.
- SoC Controller Orchestrating Data Processing Engines via On-Chip Network
An integrated controller manages data processing engine arrays via an on-chip network, eliminating off-chip PCIe bottlenecks to accelerate communication speed.
- Hybrid SLC-MLC Memory Data Management via Priority-Based Segmentation
Segmenting data into hot and cold groups with assigned flush priorities reduces merge operations and erase counts in hybrid SLC-MLC memory systems.
- Memory Controller Speculative Read Execution
A memory controller predicts sequential read commands to initiate speculative execution of subsequent data requests.
- Virtual Machine Allocation in NUMA Systems
An information processing apparatus calculates availability evaluation values to optimize virtual machine distribution across nodes.
- TLB Partitioning with Victim Buffer for Hot Set Management
Segmenting TLB ways into primary and victim roles reduces miss rates caused by hot set hash collisions while preserving fixed circuit area.
- Real-Time Stack Protection via MPU Read-Only Enforcement
Hardware enforcement of read-only return address locations prevents real-time stack buffer overflow attacks without canary memory overhead.
- Memory Controller Garbage Collection Strategy for Erase Block Disturb
Switching garbage collection granularity between erase block and physical block levels reduces write amplification while extending the erase suspend window.
- Heterogeneous Parallel System Memory Permission Control
A parallel system manages memory permissions to control data transfer between main and accelerator devices.
- Reference Counting Overhead Reduction via Segmented Local and Global Counters
Segmented reference counters track thread references to reduce locking overhead, improving system performance by minimizing instruction latency.
- SSD Block Vulnerability Prediction for Wear Leveling
Calculating block vulnerability factors directs write loads away from degraded SSD segments, reducing premature failure risks.
- Nonvolatile Memory Cache Pinning for SSD Boot Performance
Pinning a nonvolatile memory cache to operating system address ranges resolves poor initial performance in solid state drives before usage metrics stabilize.
- Memory Controller Buffer Management for Random Read Optimization
A memory controller dynamically adjusts buffer capacity ratios for multi-level mapping tables during random read operations.
- Memory Subsystem Garbage Collection Parameter Adjustment
A memory sub-system adjusts garbage collection parameters by criticality level, reducing battery power consumption while maintaining data integrity.
- Remote Data Integrity Verification via Separate Hash Storage
Separate hash storage verifies remote data integrity without appending extra data, resolving protocol compatibility constraints.
- Resource-Specific Cache Flushes for GPU Pipeline Stalling
Segmented cache structures enable resource-specific flushes to maintain coherence without halting the entire graphics pipeline.
- Multi-CPU Shared L2 Cache Segmentation for Latency Reduction
Segmenting the shared L2 cache into independently accessible banks eliminates snooping operations, reducing process latency while maintaining power efficiency.
- Block Address Entropy Tracking for SSD Garbage Collection
A non-volatile memory system tracks block address entropy to estimate mapping table reads required for garbage collection.
- Compressed Forward Map for SSD Memory Optimization
A storage controller compresses forward maps using a sifting module to reduce memory footprint.