Flash Memory Controller Double Write Buffer for QLC Data Integrity

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Solution Overview

Problem

NAND flash controllers face issues with data integrity when writing to quad-level cell (QLC) flash memory, as incomplete page writing can result in missing or damaged data, especially due to open word line or sudden power loss, leading to compromised storage capacity and speed.

Innovation Solution

Implementing a double write operation with a flash memory controller that includes a first and second buffer memory, where data is initially stored in the first buffer memory and then transmitted to a first memory portion, and subsequently to a host memory buffer, ensuring data integrity and capacity by prioritizing the write operation and using error correction techniques.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If data is written directly to QLC flash memory without buffer storage, then write speed is improved, but data integrity deteriorates due to open word line or power loss

Engineering Contradiction:
Improvewrite speedVSAvoiddata integrity
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent applies preliminary action by storing data in a buffer memory before writing to the flash memory. This allows the system to prepare and validate data完整性 before the actual write operation, ensuring that if power is lost or word line opens, the buffer can be used to recover or complete the write operation, thus maintaining data integrity while enabling faster write speeds.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If buffer memory is used to store data before writing, then data integrity is improved, but write speed deteriorates due to additional storage step

Engineering Contradiction:
Improvedata integrityVSAvoidwrite speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent implements continuity of useful action by enabling parallel operations: while data is being written from the buffer to flash memory, the buffer can immediately receive new data from the host. This continuous flow eliminates idle time and ensures that the buffer is always productive, thereby maintaining high write speeds while preserving data integrity through the buffer mechanism.

Inventive Principle:
Principle #20Continuity of useful action

3Quantity of substance

If incomplete page writing is allowed in QLC, then storage capacity is improved, but data integrity deteriorates due to missing data

Engineering Contradiction:
Improvestorage capacityVSAvoiddata integrity
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent applies feedback by implementing a verification mechanism that checks whether page writing is complete before considering the write operation successful. The buffer memory stores the expected complete data, and after writing to flash, the system verifies integrity. If verification fails due to incomplete writing, the system can retry or correct the operation, thus ensuring data integrity while allowing the flash memory to utilize its full storage capacity.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11630604B2Methods for controlling data storage device, and associated flash memory controller
Publication Date: 2023.04.18 SILICON MOTION INC
  • US11630604B2 patent drawing
  • US11630604B2 patent drawing
  • US11630604B2 patent drawing

AI summary

The present invention provides a method for controlling a data storage device. The data storage device includes a flash memory controller and a flash memory module. The flash memory controller has a first buffer memory and a second buffer memory. The memory module has at least a first memory portion and a second memory portion. The method includes: receiving a first data from a host device; storing the first data in the first buffer memory; transmitting the first data to the first memory portion of the flash memory module from the first buffer memory; and transmitting the first data to a host memory buffer in the host device from the first buffer memory. The first data corresponds to at least a portion of a second data to be written to the second memory portion.