Memory Controller Garbage Collection Strategy for Erase Block Disturb

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Solution Overview

Problem

Existing memory systems face challenges in managing multiple erase blocks coupled to the same string, leading to increased disturb effects, bit error rates, and reduced system performance due to inefficient garbage collection and erase operations.

Innovation Solution

Implementing a memory management policy that switches between performing garbage collection at the erase block level and the physical block level, balancing P/E cycling offset management and garbage collection, to reduce write amplification and improve quality of service.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If garbage collection is performed at the erase block level, then write amplification is reduced and quality of service is improved, but bus collisions increase and erase suspend window is reduced

Engineering Contradiction:
Improvequality of serviceVSAvoiderase suspend window
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The system dynamically switches between erase block level and physical block level garbage collection based on real-time conditions. The controller monitors bus collision frequency and adjusts the garbage collection granularity accordingly, transitioning between fine-grained (erase block level) and coarse-grained (physical block level) operations to optimize both quality of service and erase suspend window.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system implements periodic switching between different garbage collection granularities. By alternating between erase block level and physical block level operations at predetermined intervals or based on monitored conditions, the system maintains a balance between reducing write amplification and preserving erase suspend window.

Inventive Principle:
Principle #19Periodic action

2Quantity of substance

If multiple erase blocks are coupled to the same string, then memory density is improved, but disturb effects and bit error rates increase

Engineering Contradiction:
Improvememory densityVSAvoiddisturb effects
Core Design Contradiction:
Quantity of substanceVSObject-affected harmful factors

Solution Approach 1:

The system segments the memory array into multiple erase blocks that can be independently managed despite sharing common strings. By implementing separate garbage collection operations for each erase block and tracking their individual P/E cycling offsets, the system isolates disturb effects to specific segments rather than propagating across the entire physical block.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The controller monitors P/E cycling offset information for each erase block and uses this feedback to manage garbage collection operations. By tracking the cumulative P/E cycles for each erase block and adjusting operations based on this information, the system reduces disturb effects on cells experiencing higher cycling rates.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS20250181501A1Memory management among multiple erase blocks coupled to a same string
Publication Date: 2025.06.05 MICRON TECHNOLOGY INC
  • US20250181501A1 patent drawing
  • US20250181501A1 patent drawing
  • US20250181501A1 patent drawing

AI summary

An apparatus can comprise a memory array comprising a plurality of physical blocks of strings of memory cells, wherein each physical block of the plurality of physical blocks comprises multiple erase blocks that are independently erasable, and wherein the multiple erase blocks within a particular physical block comprise memory cells coupled to a same string corresponding to the particular physical block. A controller can be coupled to the memory array and configured to: perform a memory management operation at an erase block level; and switch to perform the memory management operation at a physical block level.