Real-Time Stack Protection via MPU Read-Only Enforcement

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Solution Overview

Problem

Stack buffer overflow vulnerabilities allow malicious data to corrupt the subroutine stack, leading to potential security breaches and system control by hackers, with existing solutions like canaries being non-real-time and prone to brute force attacks.

Innovation Solution

Implementing a Memory Protection Unit (MPU) with new instructions (rtssp_call and rtssp_ret) that dynamically protect the topmost return address location by enforcing read-only access, using the MPU to generate a high-priority interrupt upon any attempt to write to it, thereby preventing stack corruption in real-time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If canary-based stack protection is used, then stack corruption detection capability is improved, but detection timing is delayed until function return and the system becomes vulnerable to brute force attacks

Engineering Contradiction:
Improvestack corruption detection capabilityVSAvoiddetection timing
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by setting up the protection mechanism in advance through the rtssp_call instruction, which configures the MPU to monitor the return address location before any potential corruption can occur. This eliminates the delay inherent in canary-based approaches that only detect corruption at function return, enabling real-time detection immediately when corruption attempts happen.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent replaces the software-based canary checking mechanism with a hardware-based MPU monitoring system. The MPU provides real-time hardware enforcement of read-only protection on return address locations, substituting the delayed software detection model with immediate hardware-level protection that cannot be brute-forced.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Speed

If real-time hardware protection using MPU is implemented, then detection speed and security against brute force attacks are improved, but device complexity increases

Engineering Contradiction:
Improvedetection speedVSAvoidhardware protection mechanism complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent leverages the existing MPU, which is a standard component in modern processors for memory management and protection. By utilizing this existing multi-functional hardware component for stack protection purposes through the rtssp_call and rtssp_ret instructions, the patent achieves real-time protection without adding significant device complexity, as the MPU already performs similar protection functions for other memory regions.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If canary values are stored on the stack, then stack corruption detection is enabled, but memory overhead is introduced

Engineering Contradiction:
Improvestack corruption detectionVSAvoidmemory overhead
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent extracts the protection mechanism from the stack memory space by using the MPU to monitor return address locations directly in hardware. This eliminates the need to store canary values in stack memory, removing the memory overhead while maintaining corruption detection capability through hardware-enforced read-only protection.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS10606771B2Real time stack protection
Publication Date: 2020.03.31 INFINEON TECHNOLOGIES AG
  • US10606771B2 patent drawing
  • US10606771B2 patent drawing
  • US10606771B2 patent drawing

AI summary

Methods, circuitries, and systems for real-time protection of a stack are provided. A stack protection circuitry includes interface circuitry and computation circuitry. The interface is circuitry configured to receive a return instruction from a central processing unit (CPU). The computation circuitry is configured to, in response to the return instruction, generate protection data that i) identifies a new topmost return address location that is below a current protected topmost return address location and ii) specifies read only access for the new topmost return address location. The interface circuitry is configured to provide the protection data to a memory protection unit to cause the memory protection unit to enforce a read only access restriction on the new topmost return address location.