Hybrid SLC-MLC Memory Data Management via Priority-Based Segmentation
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Solution Overview
Problem
Non-volatile memory systems face challenges in data management, particularly with the increased complexity of multi-bit memory cells, which can lead to decreased erase count and performance issues when used as main memory, and compatibility problems when used as auxiliary storage due to characteristics like rapid read speed and unit data discrepancies during erase and write operations.
Innovation Solution
A data management method that involves programming data in a predetermined unit and flushing it into a second memory device in a group-by-group manner with assigned flush priorities, optimizing the sequence based on logical sector numbers and data block associations to reduce merge operations and enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-bit memory cells (MLC) are used to increase storage capacity, then usable capacity increases, but write time increases and erase count decreases
Solution Approach 1:
The patent segments data into different types (hot data and cold data) and stores them in different memory regions (SLC cache region and MLC main storage region). This segmentation allows the system to utilize the high write speed of SLC for frequently updated hot data while maintaining the high storage capacity of MLC for less frequently accessed cold data, thereby resolving the contradiction between storage capacity and write speed.
2Quantity of substance
If multi-bit memory cells (MLC) are used to increase storage capacity, then usable capacity increases, but erase count decreases
Solution Approach 1:
The patent divides the storage system into SLC cache region and MLC main storage region. The SLC region, with higher reliability and erase count, handles hot data that requires frequent writes and erases. The MLC region, with lower erase count, stores cold data that is written and erased less frequently. This segmentation protects the MLC region from excessive erase operations, thereby maintaining its reliability while providing high storage capacity.
Solution Approach 2:
The patent implements a cache mechanism where data is first written to the SLC cache region before being gradually moved to the MLC main storage region. This preliminary action in the SLC region absorbs the wear from frequent write operations, protecting the MLC region from excessive erase cycles and preserving its reliability over time.
3Speed
If flash memory is used with rapid read speed, then read performance improves, but compatibility with file systems deteriorates due to erase/write unit discrepancies
Solution Approach 1:
The patent introduces a logical-to-physical address mapping mechanism (FTL - Flash Translation Layer) that acts as an intermediary between the file system and the flash memory's physical structure. This mediator handles the conversion between logical block addresses used by file systems and the physical page/block addresses of flash memory, resolving the incompatibility caused by different erase and write unit sizes while preserving the rapid read speed advantage.
4Productivity
If hybrid NAND flash memory devices with both SLC and MLC chips are used, then performance improves, but device complexity increases
Solution Approach 1:
The patent implements a unified storage manager that controls both SLC and MLC memory regions through a single interface and management architecture. This multi-functionality allows the system to dynamically allocate data between SLC and MLC regions based on data characteristics (hot/cold classification) while presenting a unified view to the host system, thereby improving performance without proportionally increasing device complexity.
Data Source
AI summary
A data management method includes assigning data buffered in a first memory device into at least two different groups for transfer to a second memory device. At least one of the different groups has at least two units of the data assigned thereto. The data is transferred from the first memory device to the second memory device in a sequence according to a respective priority associated with each of the different groups and in group-by-group manner such that units of the data assigned to a group having a higher priority are transferred to the second memory device prior to units of the data assigned to a group having a lower priority. Related systems and methods are also discussed.