Multi-CPU Shared L2 Cache Segmentation for Latency Reduction
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Solution Overview
Problem
In multi-CPU systems, sharing a level-2 (L2) cache between CPUs increases chip density and decreases power consumption but leads to increased process latency and performance issues due to data flushing and snooping operations when switching cache access between CPUs.
Innovation Solution
A multi-CPU data processing system with a shared L2 cache configuration, where a multiplexer selects data input and a demultiplexer passes data read from the L2 cache to the appropriate CPU controller, allowing seamless switching between CPUs without flushing or snooping the shared cache, and a power management unit controls power to each CPU and cache independently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If an L2 cache is shared between multiple CPUs, then chip density increases and power consumption decreases, but process latency increases and performance deteriorates due to data flushing and snooping operations
Solution Approach 1:
The L2 cache is divided into multiple banks, where each bank can be independently accessed by different CPUs. This segmentation allows simultaneous access to different cache banks by different CPUs, eliminating the need for sequential flushing and snooping operations while maintaining cache sharing benefits.
Solution Approach 2:
The cache system dynamically assigns access rights to different CPUs based on operational needs. The cache controller manages dynamic switching between CPUs accessing the shared cache without requiring full flushing/snooping sequences, reducing latency while maintaining coherence.
2Use of energy by stationary object
If an L2 cache is shared between multiple CPUs, then power consumption decreases, but process latency increases due to flushing and snooping operations
Solution Approach 1:
By segmenting the L2 cache into independently accessible banks, the system maintains cache sharing for power efficiency while allowing simultaneous CPU access to different banks, thereby avoiding latency-inducing flushing and snooping operations.
3Reliability
If flushing and snooping operations are performed when switching cache access between CPUs, then cache coherence is maintained, but process latency increases and performance decreases
Solution Approach 1:
The L2 cache is segmented into multiple banks that can be independently accessed by different CPUs. This segmentation allows the system to maintain cache coherence through targeted, bank-level access control rather than system-wide flushing and snooping operations, thereby preserving both coherence and performance.
Solution Approach 2:
A cache controller acts as an intermediary that manages access to the shared L2 cache banks. It coordinates between multiple CPUs and the cache banks, ensuring coherence is maintained through controlled access rather than through costly flushing and snooping operations.
Data Source
AI summary
A multi-CPU data processing system, comprising: a multi-CPU processor, comprising: a first CPU configured with at least a first core, a first cache, and a first cache controller configured to access the first cache; and a second CPU configured with at least a second core, and a second cache controller configured to access a second cache, wherein the first cache is configured from a shared portion of the second cache.