SoC Controller Orchestrating Data Processing Engines via On-Chip Network
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Solution Overview
Problem
Existing CPU and hardware accelerator systems are separate components on different substrates, relying on off-chip communication techniques like PCIe, which limits data transmission speed and integration efficiency.
Innovation Solution
A system on a chip (SoC) integrates a CPU with an array of data processing engines (DPEs) and a controller, using on-chip communication via a network-on-chip (NoC) for direct data movement and task orchestration, with a specialized controller to manage data processing and communication between the CPU and AI accelerator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If CPU and hardware accelerator are separate components on different substrates using PCIe communication, then device complexity is reduced and ease of manufacture is improved, but communication speed and data transmission efficiency deteriorate
Solution Approach 1:
The patent merges the CPU and hardware accelerator into a single integrated circuit substrate, eliminating the need for PCIe communication between separate components. The accelerator is directly coupled to the CPU through on-chip interconnects, enabling faster data transmission and reducing system complexity despite increased integration density.
2Productivity
If CPU and hardware accelerator are integrated on the same substrate, then communication efficiency and data transmission speed are improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The integrated circuit is segmented into distinct functional blocks including the CPU, accelerator with array of data processing engines, and controller. This segmentation allows for modular design and manufacturing while maintaining tight integration, enabling high productivity through on-chip communication without excessive manufacturing complexity.
3Extent of automation
If a controller is added to manage data movement in the accelerator array, then task execution efficiency is improved and CPU computational burden is reduced, but device complexity increases
Solution Approach 1:
A controller is introduced as an intermediary component between the CPU and the accelerator array. The controller manages data movement into and out of the accelerator, orchestrates task execution, and reduces the CPU's computational burden by handling control-plane operations, thereby increasing automation without excessive complexity.
Data Source
AI summary
Embodiments herein describe integrating an accelerator into a same SoC (or same chip or IC) as a CPU. The SoC also includes a controller (e.g., a microcontroller) that orchestrates data processing engines (DPEs) in the accelerator. The controller (or orchestrator) receives a task from the CPU and then configures the DPEs to perform the task. For example, the controller may divide the task into a sequence of operations that are performed by one or more of the DPEs. The controller can then report back to the CPU when the task is complete.