Multi-core Cache Coherence Protocol for Off-chip Traffic Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Multi-core processor systems face challenges in maintaining cache coherency while reducing off-chip traffic due to limited off-chip bandwidth, as cache modifications and synchronizations consume significant resources.
Innovation Solution
Implementing a cache coherence protocol that transfers ownership of cache blocks upon eviction, avoiding write-backs to main memory by designating a new owner cache, and dynamically assigning ownership to the most recently accessed cache, thereby reducing off-chip writes and improving bandwidth efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cache coherency is maintained through frequent synchronization of all cache instances with main system memory, then data consistency is improved, but off-chip bandwidth consumption increases
Solution Approach 1:
The patent implements a selective synchronization approach where only the owner cache (the cache that currently holds the most recent version of a cache line) is synchronized with main system memory, rather than synchronizing all cache instances. This local quality differentiation reduces unnecessary off-chip traffic while maintaining data consistency, as other caches can obtain updated data through on-chip owner cache responses.
Solution Approach 2:
The patent introduces an owner cache as an intermediary between multiple shared caches and main system memory. The owner cache acts as a mediator that handles all synchronization operations with main memory, while other caches communicate with the owner cache instead of directly with main memory. This intermediary structure reduces off-chip bandwidth consumption by consolidating memory access through a single owner cache.
2Reliability
If all cache instances are synchronized with main system memory, then data integrity is improved, but off-chip bandwidth resources are overutilized
Solution Approach 1:
The patent applies local quality by differentiating the role of caches: the owner cache maintains full synchronization with main system memory while other caches maintain coherence through on-chip communication with the owner cache. This selective approach ensures data integrity is maintained through the owner cache's authoritative copy while avoiding redundant synchronization of other caches with main memory.
Solution Approach 2:
The owner cache serves as an intermediary that mediates between main system memory and other shared caches. All memory synchronization operations go through the owner cache, which then propagates necessary updates to other caches through on-chip communication. This intermediary mechanism preserves data integrity while optimizing off-chip bandwidth usage.
3Loss of energy
If ownership transfer upon eviction is implemented, then off-chip write-backs are reduced, but cache coherence protocol complexity increases
Solution Approach 1:
The patent implements dynamic ownership transfer where the owner cache identity can change based on eviction events. When a cache line is evicted from the owner cache, ownership is transferred to another cache that still holds a valid copy, making the system dynamic rather than static. This dynamic ownership model reduces off-chip write-backs by ensuring the most recent cache copy becomes the new owner, but requires additional protocol logic to track and transfer ownership.
Solution Approach 2:
The patent employs feedback mechanisms where caches monitor eviction events and ownership status. When eviction occurs, the system provides feedback to transfer ownership to an appropriate cache, and this feedback loop continues to optimize the owner cache assignment. The feedback-based ownership transfer reduces off-chip traffic by intelligently redirecting future writes to the appropriate on-chip cache owner.
Data Source
Figure 1
Figure 2
Figure 3A~3B
AI summary
Technologies are generally described herein for maintaining cache coherency within a multi-core processor. A first cache entry to be evicted from a first cache may be identified. The first cache entry may include a block of data and a first tag indicating an owned state. An owner eviction message for the first cache entry may be broadcasted from the first cache. A second cache entry in a second cache may be identified. The second cache entry may include the block of data and a second tag indicating a shared state. The broadcasted owner eviction message may be detected with the second cache. An ownership acceptance message for the second cache entry may be broadcasted from the second cache. The broadcasted ownership acceptance message may be detected with the first cache. The second tag in the second cache entry may be transformed from the shared state to the owned state.