Memory Systems TRIZ Cases
- Thread-local byte counting for multi-threaded garbage collection
Thread-local arrays track allocation bytes without locks, reducing garbage collection delays in multi-threaded systems.
- HS-MMC Interface ATA Translation for HDD Capacity
HS-MMC physical interface harmonizes with ATA protocol to transfer data, lifting the 4 GByte capacity restriction on mass storage devices.
- Virtual Machine Swap Memory Segmentation and Removal
Separating swap files into dedicated storage allows periodic wiping upon events, reducing disk backup complexity and lowering overall storage costs.
- Memory Backup Controller Change Log for Flash Wear Reduction
A memory backup controller records data block identifications in a change log to track modifications before copying.
- Inclusive Cache Eviction Using Core Bits to Reduce Coherency Traffic
A caching technique uses core bits and modified LRU protocols to manage cache line evictions in inclusive hierarchies.
- Multi-core Cache Coherence Protocol for Off-chip Traffic Reduction
A cache coherence protocol transfers ownership of evicted blocks to avoid write-backs.
- Queue Demultiplexor Size Grouping for Storage I/O Bottlenecks
Size-based queue grouping eliminates arbitration logic and prevents small requests from blocking larger ones in storage controllers.
- Memory Controller Global Random Area Management
A memory controller configures global random areas using physical units from data and free zones to store updated information.
- Focused Grammar Generative Programming for Symbolic Regression
Focused grammars guide symbolic regression by modifying search parameters based on performance feedback to overcome local minima.
- Virtual Machine ISA Translation Layer for Mixed-Mode Execution
A virtual machine execution layer translates native libraries across instruction set architectures to enable platform-independent application deployment.
- Deinterleaving Device Memory Segmentation for Data Recombination
Segmenting memory into variable lengths with dynamic pointers simplifies data recombination, reducing computational complexity and hardware requirements.
- Aspect-Oriented Asynchronous Caching for Stateful Applications
Automated caching tool using aspect-oriented programming executes asynchronous functions to store stateful information without modifying source code.
- Cache Coherency Logic for Shared Memory Write Access
Cache coherency logic bypasses cache update paths for shared memory writes, reducing complexity and power consumption while maintaining data coherence.
- Cross-Language Type Inference Without Executable Regeneration
Query engines extract data typing information from internal compiler structures to support cross-language development operations.
- Runtime Library Dispatch for Heterogeneous Multiprocessor Systems
A runtime library dispatches parallel computations to hardware-specific variants across heterogeneous cores.
- Virtual Service Layer for Active-Active Data Replication
A virtual service layer enables active-active replication across sites.
- Memory Bank Diversity via Request Splitting and Arbitration
A memory management method splits access requests into sub-requests targeting different banks to increase bank diversity.
- Compact Instruction Set Encoding for Processor Decode Units
Dynamic opcode field width resolves the trade-off between limited instruction sets and restricted operand space in fixed-width formats.
- Automatic Native Image Generation Service
An automatic native generation service monitors application libraries to compile intermediate language formats into optimized native images.
- State Component for Program State Snapshot and Restoration
A state component saves program states as snapshots, enabling efficient rollback without re-execution.
- Memory Access Units for Pixel Data Alignment
Processor segments data into minimum blocks and arranges adjacent pixel lines to minimize memory bandwidth requirements.
- Storage Apparatus Rearranging Data Groups for Sequential Disk Access
A storage apparatus rearranges data groups based on target positions before transmission to optimize sequential disk access patterns.
- Dynamic Parallel Processing Control for Neural Network Power Management
A semiconductor device adjusts multiply-accumulate unit count based on input data logic level matching to optimize processing throughput.