Inclusive Cache Eviction Using Core Bits to Reduce Coherency Traffic
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Solution Overview
Problem
Prior art cache line replacement algorithms in inclusive cache hierarchies do not consider the impact of evictions on coherency traffic among lower level caches, leading to increased inter-cache traffic and performance penalties in multi-core processors and multi-processor systems.
Innovation Solution
A caching technique that takes into account the coherency traffic among cache levels by using core bits to indicate shared cache lines and a modified LRU replacement protocol to select cache ways for eviction, minimizing unnecessary lower level cache evictions and optimizing cache replacement based on coherency traffic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If standard LRU replacement protocol is used in upper level cache, then cache replacement is simple and fast, but inter-cache traffic increases due to unnecessary evictions in lower level caches
Solution Approach 1:
The patent applies preliminary action by setting up core bits in advance for each cache way in the upper level cache, indicating which lower level caches would be affected by an eviction. Before performing an eviction, the modified LRU protocol checks these pre-configured core bits to predict the number of lower level cache invalidations required, allowing the system to choose eviction targets that minimize inter-cache traffic while maintaining simple and fast replacement operations.
2Quantity of substance
If cache lines are evicted from upper level cache to make space for new data, then cache capacity is maintained, but corresponding cache lines in lower level caches become invalidated causing performance penalties
Solution Approach 1:
The patent implements feedback by using core bits that provide information about the relationship between upper level cache ways and lower level caches. The modified LRU replacement protocol uses this feedback to make informed eviction decisions, selecting cache ways for eviction that have fewer core bits set, thereby minimizing the number of lower level cache invalidations and reducing performance penalties while maintaining cache capacity.
3Speed
If inclusive cache hierarchy is used to balance performance and size, then frequently used data is stored in fast smaller cache, but evictions in upper level cache cause coherency maintenance traffic in lower level caches
Solution Approach 1:
The patent applies local quality by differentiating between cache ways based on their coherency relationships with lower level caches. Each cache way in the upper level cache has associated core bits that indicate its specific relationship with lower level caches. The modified LRU protocol uses this localized information to make targeted eviction decisions, reducing overall coherency management complexity while maintaining the performance benefits of the inclusive cache hierarchy.
Data Source
AI summary
A technique for intelligently evicting cache lines within an inclusive cache architecture. More particularly, embodiments of the invention relate to a technique to evict cache lines within an inclusive cache hierarchy based on the cache coherency traffic generated between an upper level cache and lower level caches.