Memory Access Units for Pixel Data Alignment
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Solution Overview
Problem
Conventional memory access methods result in increased overhead and bandwidth burdens due to non-boundary aligned data requests, leading to delayed processing speed and reduced system performance, especially in image processing devices.
Innovation Solution
A method that checks local memory for data blocks and generates optimized memory access requests using minimum memory access units to minimize overhead, arranging data in configurations that optimize memory bandwidth, such as grouping adjacent lines of pixel data to define a single line, thereby reducing the number of memory blocks required for access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If data is stored in conventional two-dimensional arrays in external memory, then data can be accessed similarly to display arrangement, but memory bandwidth requirements increase resulting in overhead and delayed processing speed
Solution Approach 1:
The patent segments memory access units into minimum blocks (e.g., 4x4 pixel blocks) that can be independently managed. This segmentation allows the system to request only the specific minimum blocks containing desired pixels rather than entire conventional memory blocks, reducing the total number of blocks accessed and optimizing memory bandwidth utilization.
Solution Approach 2:
The patent transforms the conventional two-dimensional memory arrangement into a three-dimensional structure by adding the dimension of multiple memory banks or layers. This allows pixels to be distributed across different memory banks in a way that enables parallel access and reduces conflicts, thereby improving memory bandwidth efficiency without sacrificing the two-dimensional display mapping.
2Adaptability or versatility
If non-boundary aligned memory requests are made repeatedly, then data access flexibility is maintained, but bandwidth requirements increase and system performance reduces
Solution Approach 1:
The patent merges multiple small non-aligned memory requests into a single optimized request by identifying the minimum memory blocks that contain all desired pixels. Instead of making separate requests for each pixel or small group, the system combines these into unified requests for minimum blocks, reducing the total number of memory transactions and improving system performance while maintaining access flexibility.
Solution Approach 2:
The patent performs preliminary analysis of memory access patterns to pre-identify the minimum memory blocks that will be needed. By determining the optimal set of minimum blocks in advance, the system can prepare and execute memory requests more efficiently, reducing latency and improving overall productivity while maintaining the ability to handle non-aligned access patterns.
3Measurement precision
If memory blocks are reduced in size using conventional methods, then data access precision is improved, but memory overhead doubles resulting in 100% increase in bandwidth burden
Solution Approach 1:
The patent changes the fundamental parameter of memory block size from conventional large blocks to minimum blocks (e.g., 4x4 pixels). This parameter change enables precise access to small groups of pixels without the overhead penalty, because the minimum block size is optimized to match the actual data access patterns. The system requests only the minimum blocks containing desired pixels, achieving both precision and reduced overhead.
Data Source
AI summary
A device and methods are provided for accessing memory. In one embodiment, a method includes receiving a request for data stored in a device, checking a local memory for data based on the request to determine if one or more blocks of data associated with the request are stored in the local memory, and generating a memory access request for one or more blocks of data stored in a memory of the device based when one or more blocks of data are not stored in the local memory. In one embodiment, data stored in memory of the device may be arranged in a configuration to include a plurality of memory access units each having adjacent lines of pixel data to define a single line of memory within the memory access units. Memory access units may be configured based on memory type and may reduce the number of undesired pixels read.