Dynamic Parallel Processing Control for Neural Network Power Management
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Solution Overview
Problem
As the number of parallel processing units in semiconductor devices increases, so does power consumption, potentially exceeding allowable limits, especially when processing images with high dynamic range, leading to reduced processing capacity and increased time for neural networks.
Innovation Solution
A semiconductor device with first and second memories, n multiply-accumulate units, first and second DMA controllers, a sequence controller, and a measurement circuit, where the measurement circuit measures the degree of logic level matching/mismatching in input data and the sequence controller adjusts the number of parallel processes to maintain power within allowable limits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of parallel processings of multiply-accumulate units is increased, then processing efficiency of neural network is improved, but power consumption increases and may exceed allowable limit
Solution Approach 1:
The patent implements dynamic control of the number of parallel multiply-accumulate units based on real-time power consumption monitoring. The control unit adjusts the operational state of multiply-accumulate units according to detected power levels, enabling the system to adapt its processing capacity to current power conditions rather than operating at a fixed state.
Solution Approach 2:
The patent incorporates a power consumption detection unit that continuously monitors power usage and feeds this information back to the control unit. This feedback mechanism enables the system to detect when power consumption approaches the allowable limit and automatically reduce the number of active parallel processings accordingly.
2Use of energy by moving object
If the number of parallel processings is fixed to ensure power consumption within limit, then power consumption is controlled, but processing capacity is excessively lowered and processing time increases
Solution Approach 1:
The system dynamically adjusts the number of parallel multiply-accumulate units based on actual power consumption conditions rather than using a fixed configuration. This allows the system to maximize processing capacity when power is available and reduce capacity only when necessary to stay within power limits.
Solution Approach 2:
The patent changes the operational parameters of the neural network processing system by adjusting the number of active parallel processings based on detected power consumption levels. This parameter adjustment allows the system to optimize between processing speed and power usage according to real-time conditions.
3Productivity
If miniaturization and circuit maturation are advanced to increase number of multiply-accumulate units, then processing efficiency is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic power management for arrays of multiply-accumulate units, enabling the system to utilize the full capacity of miniaturized circuits when power is available while automatically scaling back when power limits are approached. This resolves the contradiction by making the system adaptable rather than static.
Solution Approach 2:
The system is designed to utilize up to n parallel multiply-accumulate units when power conditions permit, but operates with fewer units when power consumption approaches the allowable limit. This partial operation approach allows the system to take advantage of available processing capacity without exceeding power constraints.
Data Source
AI summary
A second memory stores a plurality of input data sets DSi composed of a plurality of pieces of input data. N multiply-accumulate units are capable of performing parallel processings, and each performs a multiply-accumulate operation on any one of the plurality of weight parameter sets and any one of the plurality of input data sets. A second DMA controller transfers the input data set from the second memory to the n multiply-accumulate units. A measurement circuit measures a degree of matching/mismatching of logic levels among the plurality of pieces of input data contained in the input data set within the memory MEM2, the sequence controller controls the number of parallel processings by the n multiply-accumulate units based on a measurement result by the measurement circuit.