Cache Coherency Logic for Shared Memory Write Access
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Solution Overview
Problem
In multi-processing systems, handling write access requests to shared memory that require both cache and shared memory updates is complex and costly, particularly for non-cacheable and write-through write access requests, due to the need for atomic updates and potential hazards like double writing, which increases complexity and power consumption.
Innovation Solution
The cache coherency logic initiates a coherency operation across all caches, including the originating processing unit's cache, to ensure data coherence and issue an update request to shared memory, decoupling cache and memory updates, thus avoiding additional complexity and hazards.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If write access requests to shared memory require both cache and shared memory updates, then data coherence is maintained, but the complexity of handling such requests increases significantly
Solution Approach 1:
The patent extracts the complexity of handling write access requests from the cache control logic by identifying and separating the specific case of write requests that require both cache and shared memory updates. By treating these requests differently - bypassing the cache update path and directly updating shared memory while still initiating coherency operations - the system removes the hazardous atomic update requirement from the cache control logic, thereby reducing its complexity while maintaining data coherence.
2Reliability
If atomic updates are performed to ensure correct behavior, then data integrity is maintained, but the power consumption increases
Solution Approach 1:
The patent removes the requirement for atomic updates from the cache control logic by extracting the shared memory update operation from the cache update path. Write requests that require both cache and shared memory updates are handled by bypassing the cache write path entirely and directly updating shared memory through the coherency interface, thereby eliminating the power-consuming atomic update mechanism while maintaining data integrity through the coherency protocol.
3Reliability
If additional logic is added to cache control to handle write through regions, then correct behavior is achieved, but the complexity of cache control logic increases
Solution Approach 1:
The patent extracts the handling of write through region requests from the cache control logic by creating a separate processing path. When a write request targets a write through region or requires shared memory updates, the system bypasses the cache control logic's update path entirely and routes the request directly to shared memory through the coherency interface, thereby achieving correct behavior without adding complexity to the cache control logic.
Solution Approach 2:
The patent segments the write request handling into distinct paths: one for cacheable writes that update both cache and shared memory, and another for write-through writes that bypass cache updates and directly update shared memory. This segmentation allows the cache control logic to remain simple while still handling complex write-through scenarios correctly through dedicated processing logic.
4Reliability
If cache lookups are performed for all write access requests, then data coherence is ensured, but the time to access cache increases
Solution Approach 1:
The patent applies partial action by performing cache lookups only when necessary - specifically for write requests that can update the cache. For write requests that require shared memory updates (write-through regions, non-cacheable memory), the system performs only the minimal necessary action of initiating a coherency operation without performing a full cache lookup, thereby reducing access time while maintaining coherence for the cases that require it.
Data Source
AI summary
A plurality of processing units for performing data processing operations require access to data in shared memory. Each has an associated cache storing a subset of the data for access by that processing unit. A cache coherency protocol ensures data accessed by each unit is up-to-date. Each unit issues a write access request when outputting a data value for storing in shared memory. When the write access request requires both the associated cache and the shared memory to be updated, a coherency operation is initiated within the cache coherency logic. The coherency operation is performed for all of the caches including the cache associated with the processing unit that issued the write access request in order to ensure that the data in those caches is kept coherent.