Cache Hit Detection Circuit Using Segmented Error and Comparison Units

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Solution Overview

Problem

Existing memory systems face performance delays due to slow cache memory access and increased complexity from error correction/detection capabilities, which hinder the processing unit's ability to retrieve data efficiently.

Innovation Solution

A circuit and method for fast cache memory hit detection, utilizing an error detect unit, comparison unit, and selection unit to concurrently compute error indicators and compare memory addresses, reducing logic complexity and delay by determining cache hits in a timely manner.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If error correction/detection capability is added to cache memory, then data reliability is improved, but device complexity and access delay increase

Engineering Contradiction:

Improvedata reliabilityVSAvoidlogic complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The cache tag is divided into multiple sections, each with its own error detection logic. The comparison unit is segmented to compare different portions of tags independently. This segmentation allows parallel error detection and comparison operations, reducing overall complexity while maintaining reliability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Error detection is performed preliminarily on cache tags before the comparison operation. The error detect unit checks for errors in cache tags in advance, and only tags without errors are subjected to comparison. This preliminary action prevents unnecessary comparison operations on erroneous tags, reducing overall device complexity and access delay.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If error correction/detection capability is added to cache memory, then data reliability is improved, but cache access speed deteriorates

Engineering Contradiction:

Improvedata reliabilityVSAvoidcache access speed

Core Design Contradiction:

ReliabilityVSSpeed

Solution Approach 1:

Error detection is performed preliminarily and in parallel with tag comparison. The error detect unit operates concurrently with the comparison unit, checking for errors before the comparison result is finalized. This preliminary error detection prevents access delays caused by subsequent error detection, maintaining cache access speed while ensuring data reliability.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The error detection and comparison operations are designed to occur continuously and concurrently during the cache access process. The error detect unit and comparison unit operate simultaneously, and the results are combined without interrupting the cache access flow. This continuous operation ensures that error detection does not add significant delay to cache access speed.

Inventive Principle:

Principle #20Continuity of useful action

3Reliability

If traditional error detection methods are used in cache memory, then data reliability is improved, but integrated circuit real estate and power usage increase

Engineering Contradiction:

Improvedata reliabilityVSAvoidintegrated circuit real estate

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The error detection logic is merged with the existing cache tag structure and comparison logic. The error detect unit shares resources with the comparison unit, and both units operate on the same tag data. This merging eliminates the need for separate, dedicated error detection hardware, reducing integrated circuit real estate while maintaining data reliability.

Inventive Principle:

Principle #5Merging (Combining)

4Reliability

If traditional error detection methods are used in cache memory, then data reliability is improved, but power consumption increases

Engineering Contradiction:

Improvedata reliabilityVSAvoidpower usage

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

Error detection is performed preliminarily on cache tags before full comparison operations. By detecting errors early in the process, the system可以避免 performing unnecessary comparison operations on tags with errors, thereby reducing overall power consumption while maintaining data reliability.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS8051337B2System and method for fast cache-hit detection

Publication Date: 2011.11.01 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A system and method for fast detection of cache memory hits in memory systems with error correction/detection capability is provided. A circuit for determining an in-cache status of a memory address comprises an error detect unit coupled to a cache memory, a comparison unit coupled to the cache memory, a results unit coupled to the comparison unit, and a selection unit coupled to the results unit and to the error detect unit. The error detect unit computes an indicator of errors present in data stored in the cache memory, wherein the data is related to the memory address. The comparison unit compares the data with a portion of the memory address, the results unit computes a set of possible in-cache statuses based on the comparison, and the selection unit selects the in-cache status from the set of possible in-cache statuses based on the indicator.