Cache Circuit Hit Rate Control for Main Memory Access

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Solution Overview

Problem

Conventional cache management systems face challenges in ensuring steady access to main memory during bus operation examination, as the cache hit rate varies with different types of main memory and program operations, leading to potential prolonged lack of access to main memory.

Innovation Solution

A cache circuit that includes a cache memory, a cache control circuit, and a cache memory disabling circuit, which disables cache entries based on the number of cache hits or hit rate to maintain access to main memory, ensuring steady instruction and data access.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If cache memory is used to hold instruction codes and data, then processing speed is improved, but access to main memory decreases

Engineering Contradiction:

Improveprocessing speedVSAvoidmain memory access

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The cache control circuit periodically disables cache entries based on timer interrupts to create periodic access patterns to main memory. This ensures that even though cache memory provides fast processing speed, the system periodically accesses main memory through the bus for examination purposes, resolving the contradiction between speed improvement and main memory access reliability.

Inventive Principle:

Principle #19Periodic action

2Reliability

If timer interrupt is used to disable cache entries, then main memory access is ensured, but the period must be optimally set for each main memory type

Engineering Contradiction:

Improvemain memory accessVSAvoidtimer period configuration

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The system changes the cache disable period parameter dynamically based on the detected main memory type. Different timer interrupt periods are applied for different main memory types (SRAM, SDRAM, flash ROM), allowing the system to maintain reliable main memory access without requiring manual optimization of the timer period for each memory type.

Inventive Principle:

Principle #35Parameter changes

3Reliability

If cache entries are periodically disabled, then main memory access is maintained, but cache hit rate may increase and prolong lack of access

Engineering Contradiction:

Improvemain memory accessVSAvoidcache hit rate

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The cache control circuit monitors the cache hit rate and uses this feedback information to dynamically adjust the cache disable strategy. When the cache hit rate is high, the system extends the period between cache disables or reduces the frequency of disabling, thereby maintaining reliable main memory access while avoiding excessive disruption to cache performance.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS7899992B2Cache circuit and control circuits of a cache memory

Publication Date: 2011.03.01 PANNOVA SEMIC LLC

AI summary

In the cache circuit, an instruction cache hit counter counts the number of cache hits, and an instruction memory access counter counts the number of times of instruction access. An instruction cache hit rate computation/entry disabling control circuit computes the ratio of the cache hit count to the instruction access count (cache hit rate). If the cache hit rate exceeds an instruction cache entry disabling threshold, an instruction cache control circuit disables contents of instruction cache memory.