Memory Systems TRIZ Cases
- DMA Request Handling in Virtual Memory via Temporary Block
Virtual memory manager redirects DMA transfers to a temporary block for safe data movement.
- Out-of-Order Stride Prefetcher for Irregular Access Patterns
Out-of-order stride prefetch units estimate access strides from virtual address offsets to reduce memory latency in irregular loop patterns.
- Cache Circuit Hit Rate Control for Main Memory Access
A cache circuit disables entries based on hit rates to maintain steady main memory access.
- Automated API Generation via Compiler Templates
Compiler-generated API codes minimize manual input requirements and coding errors while optimizing dispatch time through Type-Length-Value packaging.
- Flash Memory Controller RAM Multiplexing for Copy Operations
Multiplexing internal RAM between look-up tables and copy buffers reduces system costs while minimizing processing time during data transfer operations.
- Memory Controller State Machine for Shared Pin Arbitration
Autonomous state machines manage shared pin access to eliminate processor coordination overhead, reducing power consumption.
- Byte Enable Signal Generation for Hardware Compatibility
A controlling apparatus generates Byte Enable signals compatible with processing devices to ensure seamless data transmission.
- EEPROM Flashing via Management Processor
A management processor flashes EEPROMs without host involvement, eliminating backup storage needs.
- Digital Processor Mixed Pointer Size Memory Optimization
Segmenting pointers by address range reduces memory capacity and bandwidth while maintaining full logical address space coverage.